diff mbox series

[v2,1/2] common/mlx5: add meter mode definition in PRM file

Message ID 20210410073150.1873196-2-lizh@nvidia.com (mailing list archive)
State Superseded, archived
Delegated to: Raslan Darawsheh
Headers
Series Support meter PPS(packet per second) in MLX5 PMD |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Li Zhang April 10, 2021, 7:31 a.m. UTC 
  Add meter mode definitions in PRM file

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/common/mlx5/mlx5_prm.h | 8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index c6d8060bb9..efa5ae67bf 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -2297,6 +2297,13 @@  struct mlx5_ifc_flow_meter_parameters_bits {
 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
 
+enum {
+	MLX5_METER_MODE_IP_LEN = 0x0,
+	MLX5_METER_MODE_L2_LEN = 0x1,
+	MLX5_METER_MODE_L2_IPG_LEN = 0x2,
+	MLX5_METER_MODE_PKT = 0x3,
+};
+
 enum {
 	MLX5_CQE_SIZE_64B = 0x0,
 	MLX5_CQE_SIZE_128B = 0x1,
@@ -2671,6 +2678,7 @@  struct mlx5_aso_mtr_dseg {
 #define ASO_DSEG_VALID_OFFSET 31
 #define ASO_DSEG_BO_OFFSET 30
 #define ASO_DSEG_SC_OFFSET 28
+#define ASO_DSEG_MTR_MODE 24
 #define ASO_DSEG_CBS_EXP_OFFSET 24
 #define ASO_DSEG_CBS_MAN_OFFSET 16
 #define ASO_DSEG_CIR_EXP_MASK 0x1F