From patchwork Tue Apr 6 15:11:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 90734 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7DE84A0546; Tue, 6 Apr 2021 17:11:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A82791411F0; Tue, 6 Apr 2021 17:11:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 8C3711411D1 for ; Tue, 6 Apr 2021 17:11:41 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 136F07hp004267 for ; Tue, 6 Apr 2021 08:11:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=n6sxRHF0qyLReygfA6XpJiN5vRpsGIHobtURGk3feB4=; b=GkGD9kHP4WaQTCv+HVyht3OTSLk6mo/rhy18W7C5usfn6UXK36CpSoFHGIZ6Q6pVe+f1 J2UBQyBNjVO37W8W1w/hg5Upkq5QEu7YV/EW9AeKCuXOQ0Wf3rhnQVcIptXUtu6SU7Ii MGvpGyRWdaEq5OjZejJzySa20DQyuCXDPnhp4oyuvRuwwK6sVnZNONDFhPw4DoiPnWCr 87OSTS9rrqtlD7RbCyN9so+GJndG71oMFVi95xceh548DZIg0FgsfYERHrG6n5r43sy+ RgOg8hw1Vp3F9k3UMO4no5s4kuFVMYwaS89namuyDnyDVKOnjYxZQmj8oGQMza62xMU+ jg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 37r72p35gu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 06 Apr 2021 08:11:40 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Apr 2021 08:11:39 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 6 Apr 2021 08:11:39 -0700 Received: from lab-ci-142.marvell.com (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 0BFE13F7040; Tue, 6 Apr 2021 08:11:36 -0700 (PDT) From: Ashwin Sekhar T K To: CC: , , , , , , Date: Tue, 6 Apr 2021 20:41:08 +0530 Message-ID: <20210406151115.1889455-5-asekhar@marvell.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210406151115.1889455-1-asekhar@marvell.com> References: <20210305162149.2196166-1-asekhar@marvell.com> <20210406151115.1889455-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: vDRL1yyLjyENCBSgpNd2CZdpoleLZJsk X-Proofpoint-ORIG-GUID: vDRL1yyLjyENCBSgpNd2CZdpoleLZJsk X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-06_04:2021-04-01, 2021-04-06 signatures=0 Subject: [dpdk-dev] [PATCH v3 04/11] mempool/cnxk: register plt init callback X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Register the CNXk mempool plt init callback which will set the appropriate mempool ops to be used for the platform. Signed-off-by: Ashwin Sekhar T K --- drivers/mempool/cnxk/cnxk_mempool_ops.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c index 2ce1816c04..e8f64be76b 100644 --- a/drivers/mempool/cnxk/cnxk_mempool_ops.c +++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c @@ -2,6 +2,7 @@ * Copyright(C) 2021 Marvell. */ +#include #include #include "roc_api.h" @@ -169,3 +170,17 @@ cnxk_mempool_populate(struct rte_mempool *mp, unsigned int max_objs, mp, RTE_MEMPOOL_POPULATE_F_ALIGN_OBJ, max_objs, vaddr, iova, len, obj_cb, obj_cb_arg); } + +static int +cnxk_mempool_plt_init(void) +{ + if (roc_model_is_cn10k() || roc_model_is_cn9k()) + rte_mbuf_set_platform_mempool_ops("cnxk_mempool_ops"); + + return 0; +} + +RTE_INIT(cnxk_mempool_ops_init) +{ + roc_plt_init_cb_register(cnxk_mempool_plt_init); +}