From patchwork Thu Apr 1 12:37:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 90402 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 65B17A0548; Thu, 1 Apr 2021 14:43:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B7B40141265; Thu, 1 Apr 2021 14:40:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C5FA3141264 for ; Thu, 1 Apr 2021 14:40:04 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 131CQnTR001166 for ; Thu, 1 Apr 2021 05:40:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=E2A+IfeG7uLrZZ4Ohfee1/D4rLxS9cbNaeNZPZl9D64=; b=LPICHWiW22qrjBYYTqzNWP1ZqH7/JtamrErdKtbp84kIgFgy2H0s+PASL4QcWkqVzU28 QsfYwOdKO7sEzC6+0XfwhWdzHyQF0iMpfnlSLDqWTLqDwB1x61/exOWgMq/QiI1Q7tBI 6E7xJwTlPBUGBik8nQ+H7QKCI0Myg0j9R4K72HhhjEEs/+1E1iOjWx1Fy07PvR4z5IAN 4iL/Hwi3tdvHg8WtpnGi48nCnVyrjcVHWCpX+d8A1vCRVcOl50mp89IZS1YiwJxmDjx3 BAOGD2z8MFT6RShySsz1DliTaygzeT/hOznxifa84O2ZsK+uwZepynDwk0vzO8pHHd9y dw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 37n28j2dt6-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 01 Apr 2021 05:40:03 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Apr 2021 05:40:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 1 Apr 2021 05:40:02 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 2B29F3F7041; Thu, 1 Apr 2021 05:39:58 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , Date: Thu, 1 Apr 2021 18:07:54 +0530 Message-ID: <20210401123817.14348-30-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210401123817.14348-1-ndabilpuram@marvell.com> References: <20210305133918.8005-1-ndabilpuram@marvell.com> <20210401123817.14348-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: SNEdjyfIiWC6MRtbn3teZ03PYvS6aSy_ X-Proofpoint-GUID: SNEdjyfIiWC6MRtbn3teZ03PYvS6aSy_ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-01_05:2021-03-31, 2021-04-01 signatures=0 Subject: [dpdk-dev] [PATCH v3 29/52] common/cnxk: add VLAN filter support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Add helper API to support VLAN filtering and stripping on Rx and VLAN insertion on Tx. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_nix.h | 45 ++++++++ drivers/common/cnxk/roc_nix_vlan.c | 205 +++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 8 ++ 4 files changed, 259 insertions(+) create mode 100644 drivers/common/cnxk/roc_nix_vlan.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 57253e4..f975681 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -25,6 +25,7 @@ sources = files('roc_dev.c', 'roc_nix_queue.c', 'roc_nix_rss.c', 'roc_nix_stats.c', + 'roc_nix_vlan.c', 'roc_npa.c', 'roc_npa_debug.c', 'roc_npa_irq.c', diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 048a536..ba3575b 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -17,6 +17,26 @@ enum roc_nix_sq_max_sqe_sz { roc_nix_maxsqesz_w8 = NIX_MAXSQESZ_W8, }; +enum roc_nix_vlan_type { + ROC_NIX_VLAN_TYPE_INNER = 0x01, + ROC_NIX_VLAN_TYPE_OUTER = 0x02, +}; + +struct roc_nix_vlan_config { + uint32_t type; + union { + struct { + uint32_t vtag_inner; + uint32_t vtag_outer; + } vlan; + + struct { + int idx_inner; + int idx_outer; + } mcam; + }; +}; + /* Range to adjust PTP frequency. Valid range is * (-ROC_NIX_PTP_FREQ_ADJUST, ROC_NIX_PTP_FREQ_ADJUST) */ @@ -341,6 +361,31 @@ int __roc_api roc_nix_ptp_info_cb_register(struct roc_nix *roc_nix, ptp_info_update_t ptp_update); void __roc_api roc_nix_ptp_info_cb_unregister(struct roc_nix *roc_nix); +/* VLAN */ +int __roc_api +roc_nix_vlan_mcam_entry_read(struct roc_nix *roc_nix, uint32_t index, + struct npc_mcam_read_entry_rsp **rsp); +int __roc_api roc_nix_vlan_mcam_entry_write(struct roc_nix *roc_nix, + uint32_t index, + struct mcam_entry *entry, + uint8_t intf, uint8_t enable); +int __roc_api roc_nix_vlan_mcam_entry_alloc_and_write(struct roc_nix *roc_nix, + struct mcam_entry *entry, + uint8_t intf, + uint8_t priority, + uint8_t ref_entry); +int __roc_api roc_nix_vlan_mcam_entry_free(struct roc_nix *roc_nix, + uint32_t index); +int __roc_api roc_nix_vlan_mcam_entry_ena_dis(struct roc_nix *roc_nix, + uint32_t index, const int enable); +int __roc_api roc_nix_vlan_strip_vtag_ena_dis(struct roc_nix *roc_nix, + bool enable); +int __roc_api roc_nix_vlan_insert_ena_dis(struct roc_nix *roc_nix, + struct roc_nix_vlan_config *vlan_cfg, + uint64_t *mcam_index, bool enable); +int __roc_api roc_nix_vlan_tpid_set(struct roc_nix *roc_nix, uint32_t type, + uint16_t tpid); + /* MCAST*/ int __roc_api roc_nix_mcast_mcam_entry_alloc(struct roc_nix *roc_nix, uint16_t nb_entries, diff --git a/drivers/common/cnxk/roc_nix_vlan.c b/drivers/common/cnxk/roc_nix_vlan.c new file mode 100644 index 0000000..66bf8ad --- /dev/null +++ b/drivers/common/cnxk/roc_nix_vlan.c @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +static inline struct mbox * +get_mbox(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct dev *dev = &nix->dev; + + return dev->mbox; +} + +int +roc_nix_vlan_mcam_entry_read(struct roc_nix *roc_nix, uint32_t index, + struct npc_mcam_read_entry_rsp **rsp) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct npc_mcam_read_entry_req *req; + int rc = -ENOSPC; + + req = mbox_alloc_msg_npc_mcam_read_entry(mbox); + if (req == NULL) + return rc; + req->entry = index; + + return mbox_process_msg(mbox, (void **)rsp); +} + +int +roc_nix_vlan_mcam_entry_write(struct roc_nix *roc_nix, uint32_t index, + struct mcam_entry *entry, uint8_t intf, + uint8_t enable) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct npc_mcam_write_entry_req *req; + struct msghdr *rsp; + int rc = -ENOSPC; + + req = mbox_alloc_msg_npc_mcam_write_entry(mbox); + if (req == NULL) + return rc; + req->entry = index; + req->intf = intf; + req->enable_entry = enable; + mbox_memcpy(&req->entry_data, entry, sizeof(struct mcam_entry)); + + return mbox_process_msg(mbox, (void *)&rsp); +} + +int +roc_nix_vlan_mcam_entry_alloc_and_write(struct roc_nix *roc_nix, + struct mcam_entry *entry, uint8_t intf, + uint8_t priority, uint8_t ref_entry) +{ + struct npc_mcam_alloc_and_write_entry_req *req; + struct npc_mcam_alloc_and_write_entry_rsp *rsp; + struct mbox *mbox = get_mbox(roc_nix); + int rc = -ENOSPC; + + req = mbox_alloc_msg_npc_mcam_alloc_and_write_entry(mbox); + if (req == NULL) + return rc; + req->priority = priority; + req->ref_entry = ref_entry; + req->intf = intf; + req->enable_entry = true; + mbox_memcpy(&req->entry_data, entry, sizeof(struct mcam_entry)); + + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + return rc; + + return rsp->entry; +} + +int +roc_nix_vlan_mcam_entry_free(struct roc_nix *roc_nix, uint32_t index) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct npc_mcam_free_entry_req *req; + int rc = -ENOSPC; + + req = mbox_alloc_msg_npc_mcam_free_entry(mbox); + if (req == NULL) + return rc; + req->entry = index; + + return mbox_process_msg(mbox, NULL); +} + +int +roc_nix_vlan_mcam_entry_ena_dis(struct roc_nix *roc_nix, uint32_t index, + const int enable) +{ + struct npc_mcam_ena_dis_entry_req *req; + struct mbox *mbox = get_mbox(roc_nix); + int rc = -ENOSPC; + + if (enable) { + req = mbox_alloc_msg_npc_mcam_ena_entry(mbox); + if (req == NULL) + return rc; + } else { + req = mbox_alloc_msg_npc_mcam_dis_entry(mbox); + if (req == NULL) + return rc; + } + + req->entry = index; + return mbox_process_msg(mbox, NULL); +} + +int +roc_nix_vlan_strip_vtag_ena_dis(struct roc_nix *roc_nix, bool enable) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct nix_vtag_config *vtag_cfg; + int rc = -ENOSPC; + + vtag_cfg = mbox_alloc_msg_nix_vtag_cfg(mbox); + if (vtag_cfg == NULL) + return rc; + vtag_cfg->vtag_size = NIX_VTAGSIZE_T4; + vtag_cfg->cfg_type = 1; /* Rx VLAN configuration */ + vtag_cfg->rx.capture_vtag = 1; /* Always capture */ + vtag_cfg->rx.vtag_type = 0; /* Use index 0 */ + + if (enable) + vtag_cfg->rx.strip_vtag = 1; + else + vtag_cfg->rx.strip_vtag = 0; + + return mbox_process(mbox); +} + +int +roc_nix_vlan_insert_ena_dis(struct roc_nix *roc_nix, + struct roc_nix_vlan_config *vlan_cfg, + uint64_t *mcam_index, bool enable) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct nix_vtag_config *vtag_cfg; + struct nix_vtag_config_rsp *rsp; + int rc = -ENOSPC; + + vtag_cfg = mbox_alloc_msg_nix_vtag_cfg(mbox); + if (vtag_cfg == NULL) + return rc; + vtag_cfg->cfg_type = 0; /* Tx VLAN configuration */ + vtag_cfg->vtag_size = NIX_VTAGSIZE_T4; + + if (enable) { + if (vlan_cfg->type & ROC_NIX_VLAN_TYPE_INNER) { + vtag_cfg->tx.vtag0 = vlan_cfg->vlan.vtag_inner; + vtag_cfg->tx.cfg_vtag0 = true; + } + if (vlan_cfg->type & ROC_NIX_VLAN_TYPE_OUTER) { + vtag_cfg->tx.vtag1 = vlan_cfg->vlan.vtag_outer; + vtag_cfg->tx.cfg_vtag1 = true; + } + } else { + if (vlan_cfg->type & ROC_NIX_VLAN_TYPE_INNER) { + vtag_cfg->tx.vtag0_idx = vlan_cfg->mcam.idx_inner; + vtag_cfg->tx.free_vtag0 = true; + } + if (vlan_cfg->type & ROC_NIX_VLAN_TYPE_OUTER) { + vtag_cfg->tx.vtag1_idx = vlan_cfg->mcam.idx_outer; + vtag_cfg->tx.free_vtag1 = true; + } + } + + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + return rc; + + if (enable) + *mcam_index = + (((uint64_t)rsp->vtag1_idx << 32) | rsp->vtag0_idx); + + return 0; +} + +int +roc_nix_vlan_tpid_set(struct roc_nix *roc_nix, uint32_t type, uint16_t tpid) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct nix_set_vlan_tpid *tpid_cfg; + int rc = -ENOSPC; + + tpid_cfg = mbox_alloc_msg_nix_set_vlan_tpid(mbox); + if (tpid_cfg == NULL) + return rc; + tpid_cfg->tpid = tpid; + + if (type & ROC_NIX_VLAN_TYPE_OUTER) + tpid_cfg->vlan_type = NIX_VLAN_TYPE_OUTER; + else + tpid_cfg->vlan_type = NIX_VLAN_TYPE_INNER; + + return mbox_process(mbox); +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 05f4314..6eae844 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -96,6 +96,14 @@ INTERNAL { roc_nix_xstats_names_get; roc_nix_unregister_cq_irqs; roc_nix_unregister_queue_irqs; + roc_nix_vlan_insert_ena_dis; + roc_nix_vlan_mcam_entry_alloc_and_write; + roc_nix_vlan_mcam_entry_ena_dis; + roc_nix_vlan_mcam_entry_free; + roc_nix_vlan_mcam_entry_read; + roc_nix_vlan_mcam_entry_write; + roc_nix_vlan_strip_vtag_ena_dis; + roc_nix_vlan_tpid_set; roc_npa_aura_limit_modify; roc_npa_aura_op_range_set; roc_npa_ctx_dump;