From patchwork Thu Apr 1 12:37:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 90387 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4D0D8A0548; Thu, 1 Apr 2021 14:41:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A026A1411CB; Thu, 1 Apr 2021 14:39:21 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BD3CB1411FA for ; Thu, 1 Apr 2021 14:39:19 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 131CPLcT019084 for ; Thu, 1 Apr 2021 05:39:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=P7LRmI0yLEosk6T8ylKMtUDq+5SWALp6NoShf6yiOVM=; b=YuDAmBeftc9vgBggfqAkpvEaz6ubwhlpFtNBvxIA8HXLBotPH1O9FYmdO6riuZsK7600 a5oMVSM9OT1c+sW+MfNQdRORXSp+8Gp1Ri4QsxgWMwPCROP/ZgLbmwS+grxBs6c7ICVo Kglnb/uszl5/CcJ/o4W6lt+vi8zykncXIrkjR2MnZSnDLgNNt3Hmwxh1hUW0hhnVukRy 1MxeM44tWIvDJltCwSPG5ptC8RkDiI9sSLeCT3LVBPnFxPeltRU1+EvqJjMVCgNaTbYw H3t0cVfW5rzTTMepvr4zAYEfpYe5jNzC8b5y+zmcxbeJZsXvStwQysfikR5MGhDXhmKD pQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37n28jje1p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 01 Apr 2021 05:39:19 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Apr 2021 05:39:17 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 1 Apr 2021 05:39:17 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id B76FA3F7048; Thu, 1 Apr 2021 05:39:14 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , Date: Thu, 1 Apr 2021 18:07:39 +0530 Message-ID: <20210401123817.14348-15-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210401123817.14348-1-ndabilpuram@marvell.com> References: <20210305133918.8005-1-ndabilpuram@marvell.com> <20210401123817.14348-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: XA8vtMcm1NDcYHp-fi1ByKiW0FjS0Jll X-Proofpoint-ORIG-GUID: XA8vtMcm1NDcYHp-fi1ByKiW0FjS0Jll X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-01_05:2021-03-31, 2021-04-01 signatures=0 Subject: [dpdk-dev] [PATCH v3 14/52] common/cnxk: add npa performance counter support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ashwin Sekhar T K Add APIs to read NPA performance counters. Signed-off-by: Ashwin Sekhar T K --- drivers/common/cnxk/roc_npa.c | 50 +++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_npa.h | 37 ++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 88 insertions(+) diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index 80f5a78..f1e03b7 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -131,6 +131,56 @@ npa_aura_pool_fini(struct mbox *mbox, uint32_t aura_id, uint64_t aura_handle) return 0; } +int +roc_npa_pool_op_pc_reset(uint64_t aura_handle) +{ + struct npa_lf *lf = idev_npa_obj_get(); + struct npa_aq_enq_req *pool_req; + struct npa_aq_enq_rsp *pool_rsp; + struct ndc_sync_op *ndc_req; + struct mbox_dev *mdev; + int rc = -ENOSPC, off; + struct mbox *mbox; + + if (lf == NULL) + return NPA_ERR_PARAM; + + mbox = lf->mbox; + mdev = &mbox->dev[0]; + plt_npa_dbg("lf=%p aura_handle=0x%" PRIx64, lf, aura_handle); + + pool_req = mbox_alloc_msg_npa_aq_enq(mbox); + if (pool_req == NULL) + return rc; + pool_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle); + pool_req->ctype = NPA_AQ_CTYPE_POOL; + pool_req->op = NPA_AQ_INSTOP_WRITE; + pool_req->pool.op_pc = 0; + pool_req->pool_mask.op_pc = ~pool_req->pool_mask.op_pc; + + rc = mbox_process(mbox); + if (rc < 0) + return rc; + + off = mbox->rx_start + + PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); + pool_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off); + + if (pool_rsp->hdr.rc != 0) + return NPA_ERR_AURA_POOL_FINI; + + /* Sync NDC-NPA for LF */ + ndc_req = mbox_alloc_msg_ndc_sync_op(mbox); + if (ndc_req == NULL) + return -ENOSPC; + ndc_req->npa_lf_sync = 1; + rc = mbox_process(mbox); + if (rc) { + plt_err("Error on NDC-NPA LF sync, rc %d", rc); + return NPA_ERR_AURA_POOL_FINI; + } + return 0; +} static inline char * npa_stack_memzone_name(struct npa_lf *lf, int pool_id, char *name) { diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index b829b23..7c6f78d 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -146,6 +146,40 @@ roc_npa_aura_op_available(uint64_t aura_handle) return reg & 0xFFFFFFFFF; } +static inline uint64_t +roc_npa_pool_op_performance_counter(uint64_t aura_handle, const int drop) +{ + union { + uint64_t u; + struct npa_aura_op_wdata_s s; + } op_wdata; + int64_t *addr; + uint64_t reg; + + op_wdata.u = 0; + op_wdata.s.aura = roc_npa_aura_handle_to_aura(aura_handle); + if (drop) + op_wdata.s.drop |= BIT_ULL(63); /* DROP */ + + addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) + + NPA_LF_POOL_OP_PC); + + reg = roc_atomic64_add_nosync(op_wdata.u, addr); + /* + * NPA_LF_POOL_OP_PC Read Data + * + * 63 49 48 48 47 0 + * ----------------------------- + * | Reserved | OP_ERR | OP_PC | + * ----------------------------- + */ + + if (reg & BIT_ULL(48) /* OP_ERR */) + return 0; + else + return reg & 0xFFFFFFFFFFFF; +} + static inline void roc_npa_aura_op_bulk_free(uint64_t aura_handle, uint64_t const *buf, unsigned int num, const int fabs) @@ -396,4 +430,7 @@ void __roc_api roc_npa_aura_op_range_set(uint64_t aura_handle, int __roc_api roc_npa_ctx_dump(void); int __roc_api roc_npa_dump(void); +/* Reset operation performance counter. */ +int __roc_api roc_npa_pool_op_pc_reset(uint64_t aura_handle); + #endif /* _ROC_NPA_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index e2c0de9..78e9686 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -19,6 +19,7 @@ INTERNAL { roc_npa_dump; roc_npa_pool_create; roc_npa_pool_destroy; + roc_npa_pool_op_pc_reset; roc_npa_pool_range_update_check; roc_plt_init;