diff mbox series

[5/5] compress/mlx5: add timestamp format support

Message ID 20210307100251.22538-6-viacheslavo@nvidia.com (mailing list archive)
State Superseded
Delegated to: Raslan Darawsheh
Headers show
Series mlx5: add timestamp format support | expand

Checks

Context Check Description
ci/Intel-compilation fail apply issues
ci/checkpatch success coding style OK

Commit Message

Slava Ovsiienko March 7, 2021, 10:02 a.m. UTC
This patch add support for the timestamp format settings for
the receive and send queues. If the firmware version x.30.256
or above is installed and the NIC timestamps are configured
with the real-time format, the default zero values for new
added values cause the queue creation reject. The patch
queries the timestamp formats supported by the hardware and
sets the configuration values in queue context accordingly.

Fixes: 8619fcd5161b ("compress/mlx5: support queue pair operations")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/compress/mlx5/mlx5_compress.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Matan Azrad March 11, 2021, 7:56 p.m. UTC | #1
From: Viacheslav Ovsiienko
> This patch add support for the timestamp format settings for the receive and
> send queues. If the firmware version x.30.256 or above is installed and the NIC
> timestamps are configured with the real-time format, the default zero values
> for new added values cause the queue creation reject. The patch queries the
> timestamp formats supported by the hardware and sets the configuration
> values in queue context accordingly.
> 
> Fixes: 8619fcd5161b ("compress/mlx5: support queue pair operations")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
diff mbox series

Patch

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 46255ab5e0..97ddfa0c34 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -43,6 +43,7 @@  struct mlx5_compress_priv {
 	void *uar;
 	uint32_t pdn; /* Protection Domain number. */
 	uint8_t min_block_size;
+	uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */
 	/* Minimum huffman block size supported by the device. */
 	struct ibv_pd *pd;
 	struct rte_compressdev_config dev_config;
@@ -245,6 +246,9 @@  mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 		goto err;
 	}
 	sq_attr.cqn = qp->cq.cq->id;
+	/* Check whether timestamp format selection supported in FW. */
+	if (priv->sq_ts_format != MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR)
+		sq_attr.ts_format = MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
 	ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,
 				  socket_id);
 	if (ret != 0) {
@@ -814,6 +818,7 @@  mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv,
 	priv->pci_dev = pci_dev;
 	priv->cdev = cdev;
 	priv->min_block_size = att.compress_min_block_size;
+	priv->sq_ts_format = att.sq_ts_format;
 	if (mlx5_compress_hw_global_prepare(priv) != 0) {
 		rte_compressdev_pmd_destroy(priv->cdev);
 		claim_zero(mlx5_glue->close_device(priv->ctx));