From patchwork Sat Mar 6 16:29:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 88667 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C7B55A0548; Sat, 6 Mar 2021 17:34:35 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 66EA222A4F4; Sat, 6 Mar 2021 17:31:34 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3DBD222A4BF for ; Sat, 6 Mar 2021 17:31:33 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 126GPXiJ025580 for ; Sat, 6 Mar 2021 08:31:32 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=j/KkbPv/PWB2peH2dpweqkQv/0yGZCGk0u9cNJd197k=; b=UMBJsj3LT2OFo3sA+JtLluZ66BN6Uz9kRmN/BfcZ2DHzDEupfEQA2j1F0hRjCDwwkcbr pmybjvyDyFL+3DnFgcsGpR+VfU29LhHHqH9x8us0PpBA4QyalyzJ2L5DLLXPz+LI11J6 JramENwotD+mKKHKM42VpTzqkoPVdQqZHX0auPi8XhjGBjT/pan/ctVEyRrqzcakVVx9 HNokaYZWFaAugjFOOSk4R8I+tcssOPMZJ78c2Zza7QWzwcc2Y0+EuPqQFUmLXjM9Eu6I pB/OiyATqFpX1cJagejo536+MAWEwREVA76xXtLwd2RvahFyXzWHmt2C6C2SUHOo503p rw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3747yurey8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 06 Mar 2021 08:31:32 -0800 Received: from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Mar 2021 08:31:31 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Mar 2021 08:31:30 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 6 Mar 2021 08:31:30 -0800 Received: from BG-LT7430.marvell.com (unknown [10.193.68.121]) by maili.marvell.com (Postfix) with ESMTP id A06743F7041; Sat, 6 Mar 2021 08:31:28 -0800 (PST) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: , Date: Sat, 6 Mar 2021 21:59:30 +0530 Message-ID: <20210306162942.6845-26-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210306162942.6845-1-pbhagavatula@marvell.com> References: <20210306162942.6845-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-06_08:2021-03-03, 2021-03-06 signatures=0 Subject: [dpdk-dev] [PATCH 25/36] event/cnxk: add devargs for chunk size and rings X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add devargs to control default chunk size and max numbers of timer rings to attach to a given RVU PF. Example: --dev "0002:1e:00.0,tim_chnk_slots=1024" --dev "0002:1e:00.0,tim_rings_lmt=4" Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 23 +++++++++++++++++++++++ drivers/event/cnxk/cn10k_eventdev.c | 4 +++- drivers/event/cnxk/cn9k_eventdev.c | 4 +++- drivers/event/cnxk/cnxk_tim_evdev.c | 14 +++++++++++++- drivers/event/cnxk/cnxk_tim_evdev.h | 4 ++++ 5 files changed, 46 insertions(+), 3 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index 9e14f99f2..05dcf06f4 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -103,6 +103,29 @@ Runtime Config Options -a 0002:0e:00.0,tim_disable_npa=1 +- ``TIM modify chunk slots`` + + The ``tim_chnk_slots`` devargs can be used to modify number of chunk slots. + Chunks are used to store event timers, a chunk can be visualised as an array + where the last element points to the next chunk and rest of them are used to + store events. TIM traverses the list of chunks and enqueues the event timers + to SSO. The default value is 255 and the max value is 4095. + + For example:: + + -a 0002:0e:00.0,tim_chnk_slots=1023 + +- ``TIM limit max rings reserved`` + + The ``tim_rings_lmt`` devargs can be used to limit the max number of TIM + rings i.e. event timer adapter reserved on probe. Since, TIM rings are HW + resources we can avoid starving other applications by not grabbing all the + rings. + + For example:: + + -a 0002:0e:00.0,tim_rings_lmt=5 + Debugging Options ----------------- diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 807e666d3..a5a614196 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -503,4 +503,6 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" CN10K_SSO_GW_MODE "=" - CNXK_TIM_DISABLE_NPA "=1"); + CNXK_TIM_DISABLE_NPA "=1" + CNXK_TIM_CHNK_SLOTS "=" + CNXK_TIM_RINGS_LMT "="); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 3e27fce4a..cfea3723a 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -572,4 +572,6 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" CN9K_SSO_SINGLE_WS "=1" - CNXK_TIM_DISABLE_NPA "=1"); + CNXK_TIM_DISABLE_NPA "=1" + CNXK_TIM_CHNK_SLOTS "=" + CNXK_TIM_RINGS_LMT "="); diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 6bbfadb25..07ec57fd2 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -253,6 +253,10 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev) rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag, &dev->disable_npa); + rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value, + &dev->chunk_slots); + rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value, + &dev->min_ring_cnt); rte_kvargs_free(kvlist); } @@ -278,6 +282,7 @@ cnxk_tim_init(struct roc_sso *sso) cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev); dev->tim.roc_sso = sso; + dev->tim.nb_lfs = dev->min_ring_cnt; rc = roc_tim_init(&dev->tim); if (rc < 0) { plt_err("Failed to initialize roc tim resources"); @@ -285,7 +290,14 @@ cnxk_tim_init(struct roc_sso *sso) return; } dev->nb_rings = rc; - dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ; + + if (dev->chunk_slots && dev->chunk_slots <= CNXK_TIM_MAX_CHUNK_SLOTS && + dev->chunk_slots >= CNXK_TIM_MIN_CHUNK_SLOTS) { + dev->chunk_sz = + (dev->chunk_slots + 1) * CNXK_TIM_CHUNK_ALIGNMENT; + } else { + dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ; + } } void diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 8c21ab1fe..6208c150a 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -34,6 +34,8 @@ #define CN9K_TIM_MIN_TMO_TKS (256) #define CNXK_TIM_DISABLE_NPA "tim_disable_npa" +#define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots" +#define CNXK_TIM_RINGS_LMT "tim_rings_lmt" struct cnxk_tim_evdev { struct roc_tim tim; @@ -42,6 +44,8 @@ struct cnxk_tim_evdev { uint32_t chunk_sz; /* Dev args */ uint8_t disable_npa; + uint16_t chunk_slots; + uint16_t min_ring_cnt; }; enum cnxk_tim_clk_src {