From patchwork Sat Mar 6 16:29:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 88643 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7743DA0548; Sat, 6 Mar 2021 17:30:21 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5B56A22A391; Sat, 6 Mar 2021 17:30:21 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id E34DA4014D for ; Sat, 6 Mar 2021 17:30:19 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 126GRI2N027863; Sat, 6 Mar 2021 08:30:16 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=RHZOcD1zk/MbuGUXYz5ZAmMWk4ERXuQIcIWEhTNm3aQ=; b=I+MhxRsc837hTzwdyHtOpVubsH85HWA0mphwQ7+n43ddYOMwT37QTVTeWQcQsxXONapQ sCETG92yfBW7ldv0wfp1ooRbliRiau1lB/f8IJ+fO+23gPkOM3/Scj0Fmh1zbWSzxAlv gGajVPOhY3yTNW8WEH0K30GjC2tLmRsW6JOwtxNpIRQAsJFlESSz8UXs4FnircWGdN+y Wyzzptbtj2pjqkxJUFV+zo1SGIrWKFk3NAk0HvJL3fImIWXVVSYIjU/A3UaHeDWNqequ HcuuUEY8mABzOSET73nRxXuXyg4N1F5H6Q7T174kizZQPaqtLfqdoWVZWfMIvSGtuVU/ Xw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3747yureuu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 06 Mar 2021 08:30:16 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Mar 2021 08:30:14 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 6 Mar 2021 08:30:14 -0800 Received: from BG-LT7430.marvell.com (unknown [10.193.68.121]) by maili.marvell.com (Postfix) with ESMTP id CB2023F703F; Sat, 6 Mar 2021 08:30:11 -0800 (PST) From: To: , Thomas Monjalon , "Pavan Nikhilesh" , Shijith Thotton , Ray Kinsella , Neil Horman , "Anatoly Burakov" CC: , Date: Sat, 6 Mar 2021 21:59:06 +0530 Message-ID: <20210306162942.6845-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210306162942.6845-1-pbhagavatula@marvell.com> References: <20210306162942.6845-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-06_08:2021-03-03, 2021-03-06 signatures=0 Subject: [dpdk-dev] [PATCH 01/36] event/cnxk: add build infra and device setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add meson build infra structure along with the event device SSO initialization and teardown functions. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- MAINTAINERS | 6 +++ doc/guides/eventdevs/cnxk.rst | 55 ++++++++++++++++++++++++ doc/guides/eventdevs/index.rst | 1 + drivers/event/cnxk/cnxk_eventdev.c | 68 ++++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 39 +++++++++++++++++ drivers/event/cnxk/meson.build | 13 ++++++ drivers/event/cnxk/version.map | 3 ++ drivers/event/meson.build | 2 +- 8 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 doc/guides/eventdevs/cnxk.rst create mode 100644 drivers/event/cnxk/cnxk_eventdev.c create mode 100644 drivers/event/cnxk/cnxk_eventdev.h create mode 100644 drivers/event/cnxk/meson.build create mode 100644 drivers/event/cnxk/version.map diff --git a/MAINTAINERS b/MAINTAINERS index e341bc81d..89c23c49c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1211,6 +1211,12 @@ M: Jerin Jacob F: drivers/event/octeontx2/ F: doc/guides/eventdevs/octeontx2.rst +Marvell OCTEON CNXK +M: Pavan Nikhilesh +M: Shijith Thotton +F: drivers/event/cnxk/ +F: doc/guides/eventdevs/cnxk.rst + NXP DPAA eventdev M: Hemant Agrawal M: Nipun Gupta diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst new file mode 100644 index 000000000..e94225bd3 --- /dev/null +++ b/doc/guides/eventdevs/cnxk.rst @@ -0,0 +1,55 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2021 Marvell International Ltd. + +OCTEON CNXK SSO Eventdev Driver +========================== + +The SSO PMD (**librte_event_cnxk**) and provides poll mode +eventdev driver support for the inbuilt event device found in the +**Marvell OCTEON CNXK** SoC family. + +More information about OCTEON CNXK SoC can be found at `Marvell Official Website +`_. + +Supported OCTEON CNXK SoCs +-------------------------- + +- CN9XX +- CN10XX + +Features +-------- + +Features of the OCTEON CNXK SSO PMD are: + +- 256 Event queues +- 26 (dual) and 52 (single) Event ports on CN10XX +- 52 Event ports on CN9XX +- HW event scheduler +- Supports 1M flows per event queue +- Flow based event pipelining +- Flow pinning support in flow based event pipelining +- Queue based event pipelining +- Supports ATOMIC, ORDERED, PARALLEL schedule types per flow +- Event scheduling QoS based on event queue priority +- Open system with configurable amount of outstanding events limited only by + DRAM +- HW accelerated dequeue timeout support to enable power management + +Prerequisites and Compilation procedure +--------------------------------------- + + See :doc:`../platform/cnxk` for setup information. + +Debugging Options +----------------- + +.. _table_octeon_cnxk_event_debug_options: + +.. table:: OCTEON CNXK event device debug options + + +---+------------+-------------------------------------------------------+ + | # | Component | EAL log command | + +===+============+=======================================================+ + | 1 | SSO | --log-level='pmd\.event\.cnxk,8' | + +---+------------+-------------------------------------------------------+ diff --git a/doc/guides/eventdevs/index.rst b/doc/guides/eventdevs/index.rst index f5b69b39d..00203e0f0 100644 --- a/doc/guides/eventdevs/index.rst +++ b/doc/guides/eventdevs/index.rst @@ -11,6 +11,7 @@ application through the eventdev API. :maxdepth: 2 :numbered: + cnxk dlb dlb2 dpaa diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c new file mode 100644 index 000000000..b7f9c81bd --- /dev/null +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#include "cnxk_eventdev.h" + +int +cnxk_sso_init(struct rte_eventdev *event_dev) +{ + const struct rte_memzone *mz = NULL; + struct rte_pci_device *pci_dev; + struct cnxk_sso_evdev *dev; + int rc; + + mz = rte_memzone_reserve(CNXK_SSO_MZ_NAME, sizeof(uint64_t), + SOCKET_ID_ANY, 0); + if (mz == NULL) { + plt_err("Failed to create eventdev memzone"); + return -ENOMEM; + } + + dev = cnxk_sso_pmd_priv(event_dev); + pci_dev = container_of(event_dev->dev, struct rte_pci_device, device); + dev->sso.pci_dev = pci_dev; + + *(uint64_t *)mz->addr = (uint64_t)dev; + + /* Initialize the base cnxk_dev object */ + rc = roc_sso_dev_init(&dev->sso); + if (rc < 0) { + plt_err("Failed to initialize RoC SSO rc=%d", rc); + goto error; + } + + dev->is_timeout_deq = 0; + dev->min_dequeue_timeout_ns = USEC2NSEC(1); + dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF); + dev->max_num_events = -1; + dev->nb_event_queues = 0; + dev->nb_event_ports = 0; + + return 0; + +error: + rte_memzone_free(mz); + return rc; +} + +int +cnxk_sso_fini(struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + /* For secondary processes, nothing to be done */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + roc_sso_rsrc_fini(&dev->sso); + roc_sso_dev_fini(&dev->sso); + + return 0; +} + +int +cnxk_sso_remove(struct rte_pci_device *pci_dev) +{ + return rte_event_pmd_pci_remove(pci_dev, cnxk_sso_fini); +} diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h new file mode 100644 index 000000000..148b327a1 --- /dev/null +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#ifndef __CNXK_EVENTDEV_H__ +#define __CNXK_EVENTDEV_H__ + +#include + +#include + +#include "roc_api.h" + +#define USEC2NSEC(__us) ((__us)*1E3) + +#define CNXK_SSO_MZ_NAME "cnxk_evdev_mz" + +struct cnxk_sso_evdev { + struct roc_sso sso; + uint8_t is_timeout_deq; + uint8_t nb_event_queues; + uint8_t nb_event_ports; + uint32_t min_dequeue_timeout_ns; + uint32_t max_dequeue_timeout_ns; + int32_t max_num_events; +} __rte_cache_aligned; + +static inline struct cnxk_sso_evdev * +cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev) +{ + return event_dev->data->dev_private; +} + +/* Common ops API. */ +int cnxk_sso_init(struct rte_eventdev *event_dev); +int cnxk_sso_fini(struct rte_eventdev *event_dev); +int cnxk_sso_remove(struct rte_pci_device *pci_dev); + +#endif /* __CNXK_EVENTDEV_H__ */ diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build new file mode 100644 index 000000000..110b45188 --- /dev/null +++ b/drivers/event/cnxk/meson.build @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2021 Marvell International Ltd. +# + +if not is_linux or not dpdk_conf.get('RTE_ARCH_64') + build = false + reason = 'only supported on 64-bit Linux' + subdir_done() +endif + +sources = files('cnxk_eventdev.c') + +deps += ['bus_pci', 'common_cnxk', 'net_cnxk'] diff --git a/drivers/event/cnxk/version.map b/drivers/event/cnxk/version.map new file mode 100644 index 000000000..ee80c5172 --- /dev/null +++ b/drivers/event/cnxk/version.map @@ -0,0 +1,3 @@ +INTERNAL { + local: *; +}; diff --git a/drivers/event/meson.build b/drivers/event/meson.build index a49288a5d..583ebbc9c 100644 --- a/drivers/event/meson.build +++ b/drivers/event/meson.build @@ -5,7 +5,7 @@ if is_windows subdir_done() endif -drivers = ['dlb', 'dlb2', 'dpaa', 'dpaa2', 'octeontx2', 'opdl', 'skeleton', 'sw', +drivers = ['cnxk', 'dlb', 'dlb2', 'dpaa', 'dpaa2', 'octeontx2', 'opdl', 'skeleton', 'sw', 'dsw'] if not (toolchain == 'gcc' and cc.version().version_compare('<4.8.6') and dpdk_conf.has('RTE_ARCH_ARM64'))