From patchwork Fri Mar 5 13:39:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 88573 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7CF7BA0547; Fri, 5 Mar 2021 14:47:51 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B6ADD22A479; Fri, 5 Mar 2021 14:41:50 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 5358322A477 for ; Fri, 5 Mar 2021 14:41:49 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 125DelDb001639 for ; Fri, 5 Mar 2021 05:41:48 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=7Csh76D7E9zqyr5yXxSf1rCja1+ze3ZYExQnmnjFhIA=; b=WZKbB0b6Nx6WfYOEdE6dteTuPESbkEFRvJw5DZizqGkTEI+Q7C4LfL/JNy1qBh/5nalo bBlgrehfm54FDuTgG7w4WIQc26o6Evash1hVsEP1cH8o+mLR4NN/21diBvWbpjBEuImT iSREudT/xwFNDOQkVsbu3oMok+23a3IYpYNlMpOgzO4+445LJUQFImw203eKMXGof0z0 pfWCfNox4uFWKQoYGe9egZ1NiS612HpciNFsqlKMSROIz+4/LF9GgKT0L6twyxQhT75x O2YeGQdyolUXiNfIpAw6w72fmzmqNp1sbG8IMow1V9HW3FEd3H9aQvjTktQvB5Sqe36q bQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 372s2umrt4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 05 Mar 2021 05:41:48 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 5 Mar 2021 05:41:46 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 5 Mar 2021 05:41:46 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 7AC8B3F703F; Fri, 5 Mar 2021 05:41:44 -0800 (PST) From: Nithin Dabilpuram To: CC: , , , , , , Date: Fri, 5 Mar 2021 19:09:12 +0530 Message-ID: <20210305133918.8005-47-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210305133918.8005-1-ndabilpuram@marvell.com> References: <20210305133918.8005-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-05_08:2021-03-03, 2021-03-05 signatures=0 Subject: [dpdk-dev] [PATCH 46/52] common/cnxk: add sso hws interface X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add SSO HWS interface for setting/unsetting links, retrieving base address and nanoseconds to getwork timeout. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/roc_sso.c | 118 ++++++++++++++++++++++++++++++++++++- drivers/common/cnxk/roc_sso.h | 6 ++ drivers/common/cnxk/roc_sso_priv.h | 3 + drivers/common/cnxk/version.map | 4 ++ 4 files changed, 130 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index caf399b..52a7a6c 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -152,6 +152,94 @@ sso_rsrc_get(struct roc_sso *roc_sso) return 0; } +static void +sso_hws_link_modify(uintptr_t hws_base, uint16_t hwgrp, uint8_t enable) +{ + uint64_t val; + + val = hwgrp; + val |= 0ULL << 12; /* SET 0 */ + val |= 0x8000800080000000; /* Do not modify rest of the masks */ + val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */ + + plt_write64(val, hws_base + SSOW_LF_GWS_GRPMSK_CHG); +} + +/* Public Functions. */ +uintptr_t +roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + + return dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12); +} + +uint64_t +roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + uint64_t current_us, current_ns, new_ns; + uintptr_t base; + + base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20); + current_us = plt_read64(base + SSOW_LF_GWS_NW_TIM); + /* From HRM, table 14-19: + * The SSOW_LF_GWS_NW_TIM[NW_TIM] period is specified in n-1 notation. + */ + current_us += 1; + + /* From HRM, table 14-1: + * SSOW_LF_GWS_NW_TIM[NW_TIM] specifies the minimum timeout. The SSO + * hardware times out a GET_WORK request within 2 usec of the minimum + * timeout specified by SSOW_LF_GWS_NW_TIM[NW_TIM]. + */ + current_us += 2; + current_ns = current_us * 1E3; + new_ns = (ns - PLT_MIN(ns, current_ns)); + new_ns = !new_ns ? 1 : new_ns; + return (new_ns * plt_tsc_hz()) / 1E9; +} + +int +roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], + uint16_t nb_hwgrp) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + struct sso *sso; + uintptr_t base; + int i; + + sso = roc_sso_to_sso_priv(roc_sso); + for (i = 0; i < nb_hwgrp; i++) { + base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12); + sso_hws_link_modify(base, hwgrp[i], true); + plt_bitmap_set(sso->link_map[hws], hwgrp[i]); + plt_sso_dbg("HWS %d Linked to HWGRP %d", hws, hwgrp[i]); + } + + return nb_hwgrp; +} + +int +roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], + uint16_t nb_hwgrp) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + struct sso *sso; + uintptr_t base; + int i; + + sso = roc_sso_to_sso_priv(roc_sso); + for (i = 0; i < nb_hwgrp; i++) { + base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12); + sso_hws_link_modify(base, hwgrp[i], false); + plt_bitmap_clear(sso->link_map[hws], hwgrp[i]); + plt_sso_dbg("HWS %d Unlinked from HWGRP %d", hws, hwgrp[i]); + } + + return nb_hwgrp; +} + int roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp) { @@ -225,8 +313,10 @@ int roc_sso_dev_init(struct roc_sso *roc_sso) { struct plt_pci_device *pci_dev; + uint32_t link_map_sz; struct sso *sso; - int rc; + void *link_mem; + int i, rc; if (roc_sso == NULL || roc_sso->pci_dev == NULL) return SSO_ERR_PARAM; @@ -249,12 +339,38 @@ roc_sso_dev_init(struct roc_sso *roc_sso) } rc = -ENOMEM; + sso->link_map = + plt_zmalloc(sizeof(struct plt_bitmap *) * roc_sso->max_hws, 0); + if (sso->link_map == NULL) { + plt_err("Failed to allocate memory for link_map array"); + goto rsrc_fail; + } + + link_map_sz = plt_bitmap_get_memory_footprint(roc_sso->max_hwgrp); + sso->link_map_mem = plt_zmalloc(link_map_sz * roc_sso->max_hws, 0); + if (sso->link_map_mem == NULL) { + plt_err("Failed to get link_map memory"); + goto rsrc_fail; + } + + link_mem = sso->link_map_mem; + for (i = 0; i < roc_sso->max_hws; i++) { + sso->link_map[i] = plt_bitmap_init(roc_sso->max_hwgrp, link_mem, + link_map_sz); + if (sso->link_map[i] == NULL) { + plt_err("Failed to allocate link map"); + goto link_mem_free; + } + link_mem = PLT_PTR_ADD(link_mem, link_map_sz); + } idev_sso_pffunc_set(sso->dev.pf_func); sso->pci_dev = pci_dev; sso->dev.drv_inited = true; roc_sso->lmt_base = sso->dev.lmt_base; return 0; +link_mem_free: + plt_free(sso->link_map_mem); rsrc_fail: rc |= dev_fini(&sso->dev, pci_dev); fail: diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index 007ad41..c4f5c40 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -30,5 +30,11 @@ int __roc_api roc_sso_dev_fini(struct roc_sso *roc_sso); int __roc_api roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp); void __roc_api roc_sso_rsrc_fini(struct roc_sso *roc_sso); +uint64_t __roc_api roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns); +int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, + uint16_t hwgrp[], uint16_t nb_hwgrp); +int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, + uint16_t hwgrp[], uint16_t nb_hwgrp); +uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws); #endif /* _ROC_SSOW_H_ */ diff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h index d629b97..f63a01d 100644 --- a/drivers/common/cnxk/roc_sso_priv.h +++ b/drivers/common/cnxk/roc_sso_priv.h @@ -13,6 +13,9 @@ struct sso_rsrc { struct sso { struct plt_pci_device *pci_dev; struct dev dev; + /* SSO link mapping. */ + struct plt_bitmap **link_map; + void *link_map_mem; } __plt_cache_aligned; enum sso_err_status { diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 5385b36..5675a39 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -174,6 +174,10 @@ INTERNAL { roc_npc_profile_name_get; roc_sso_dev_fini; roc_sso_dev_init; + roc_sso_hws_base_get; + roc_sso_hws_link; + roc_sso_hws_unlink; + roc_sso_ns_to_gw; roc_sso_rsrc_fini; roc_sso_rsrc_init;