From patchwork Thu Mar 4 10:07:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 88468 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 770F8A0561; Thu, 4 Mar 2021 11:07:42 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 40D3A22A2ED; Thu, 4 Mar 2021 11:07:19 +0100 (CET) Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by mails.dpdk.org (Postfix) with ESMTP id 4DA5822A2DF for ; Thu, 4 Mar 2021 11:07:16 +0100 (CET) X-QQ-mid: bizesmtp14t1614852431ty6ral0m Received: from jiawenwu.trustnetic.com (unknown [183.129.236.74]) by esmtp6.qq.com (ESMTP) with id ; Thu, 04 Mar 2021 18:07:11 +0800 (CST) X-QQ-SSF: 01400000000000C0D000000A0000000 X-QQ-FEAT: tvOgVvG7QYBfiukBuEe5o1P5JW6TocbON7bby9az/PrRwvYB5hXijt5WA5oIA wZay0htGhHWk1ofEOAXrVMTckwtpZ0ymMi2cTSFTi6iT2oE/WZs1jqrg9/R+IzktJ2qB2Xg OUxffCvkE3BonezBVCvQVwxuuHVCJT+iRYxMvWvLPjoEesvJRRce9t1gIZOrqNfL3CwiArv SvNycw6WqOKlZVnUwYbaGqk00bgkP64u30kPkIWhUMGtFP+QWty0plP1mmG/fMy11ryG1DM XceMGjufRd+HTDvtdA87wlgIXGTzF/IUpjG7OHE92wNuewFBC4J3cRakmO1XfnaRWkunmId RcJKIuV3gfk6I6hdI7py+dyvHq6aw== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Date: Thu, 4 Mar 2021 18:07:00 +0800 Message-Id: <20210304100700.17888-5-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20210304100700.17888-1-jiawenwu@trustnetic.com> References: <20210304100700.17888-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign5 X-QQ-Bgrelay: 1 Subject: [dpdk-dev] [PATCH 4/4] net/txgbe: fix the process of adding crypto SA X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" By register definition, Ipsec Rx IPv4 address should to be written in the reg(0). Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_ipsec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/txgbe_ipsec.c b/drivers/net/txgbe/txgbe_ipsec.c index 9f4eee408..a43b95aa2 100644 --- a/drivers/net/txgbe/txgbe_ipsec.c +++ b/drivers/net/txgbe/txgbe_ipsec.c @@ -145,11 +145,11 @@ txgbe_crypto_add_sa(struct txgbe_crypto_session *ic_session) reg_val = TXGBE_IPSRXIDX_ENA | TXGBE_IPSRXIDX_WRITE | TXGBE_IPSRXIDX_TB_IP | (ip_index << 3); if (priv->rx_ip_tbl[ip_index].ip.type == IPv4) { - wr32(hw, TXGBE_IPSRXADDR(0), 0); + uint32_t ipv4 = priv->rx_ip_tbl[ip_index].ip.ipv4; + wr32(hw, TXGBE_IPSRXADDR(0), rte_cpu_to_be_32(ipv4)); wr32(hw, TXGBE_IPSRXADDR(1), 0); wr32(hw, TXGBE_IPSRXADDR(2), 0); - wr32(hw, TXGBE_IPSRXADDR(3), - priv->rx_ip_tbl[ip_index].ip.ipv4); + wr32(hw, TXGBE_IPSRXADDR(3), 0); } else { wr32(hw, TXGBE_IPSRXADDR(0), priv->rx_ip_tbl[ip_index].ip.ipv6[0]);