From patchwork Fri Feb 19 10:14:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasesh Mody X-Patchwork-Id: 88009 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 13FCFA054A; Fri, 19 Feb 2021 11:15:29 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C878E1608DD; Fri, 19 Feb 2021 11:15:22 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 06AC91608DB for ; Fri, 19 Feb 2021 11:15:20 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 11JAF0bB019430; Fri, 19 Feb 2021 02:15:20 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=mFZQD+ViSO8Re7Fs6zq4AU0dEl0jgI1JtzbfBMGpCV8=; b=c5a2R6TDwhcA5ZGD/rWeLoPWMckD01hiiIUm+7wNglg2u9zPChVCOZl9zPTFKV6AFVqv 5H9pq278Kvj/Y/1KhUq7eAkaPARy4az8MKkbCWl7KgEMsEuc9/+wxbLrMA77bpOOzjXY CbKj07aDHow1ZWfv7X9ZseoXjLZwctDM/Ug98VhW3AT2xS1tB43TTfjsV6Enz4R7e5Dj r0MSiTyi4UwQuZ5LWSylJeIiU1WEYoVMGGDneBaoWzToWpPTVroNJjDUA7w7yFhI7Wn+ u2cAKpMpakTBha3LPDrpBYj+BfqpCd27Fucvdo9rveVU4RZOHqEWg0PoLV12M841uPvJ pw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 36sesvvtd0-7 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 19 Feb 2021 02:15:20 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 19 Feb 2021 02:15:05 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 19 Feb 2021 02:15:05 -0800 Received: from irv1user08.caveonetworks.com (unknown [10.104.116.105]) by maili.marvell.com (Postfix) with ESMTP id ADC2F3F7043; Fri, 19 Feb 2021 02:15:05 -0800 (PST) Received: (from rmody@localhost) by irv1user08.caveonetworks.com (8.14.4/8.14.4/Submit) id 11JAF5ik019203; Fri, 19 Feb 2021 02:15:05 -0800 X-Authentication-Warning: irv1user08.caveonetworks.com: rmody set sender to rmody@marvell.com using -f From: Rasesh Mody To: , CC: Rasesh Mody , , , Igor Russkikh Date: Fri, 19 Feb 2021 02:14:21 -0800 Message-ID: <20210219101422.19121-7-rmody@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210219101422.19121-1-rmody@marvell.com> References: <20210219101422.19121-1-rmody@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-02-19_04:2021-02-18, 2021-02-19 signatures=0 Subject: [dpdk-dev] [PATCH 6/7] net/qede: add support for new HW X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds PMD support for new hardware (adding new PCI IDs) 50xxx family of Marvell fastlinq adapters. The PMD version is updated to 3.0.0.1. Signed-off-by: Rasesh Mody Signed-off-by: Igor Russkikh --- drivers/net/qede/qede_debug.c | 3 +-- drivers/net/qede/qede_ethdev.c | 8 +++++++- drivers/net/qede/qede_ethdev.h | 11 +++++++---- 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/net/qede/qede_debug.c b/drivers/net/qede/qede_debug.c index 085d0532b..ca2879432 100644 --- a/drivers/net/qede/qede_debug.c +++ b/drivers/net/qede/qede_debug.c @@ -8099,8 +8099,7 @@ void qed_dbg_pf_init(struct ecore_dev *edev) /* Debug values are after init values. * The offset is the first dword of the file. */ - /* TBD: change hardcoded value to offset from FW file */ - dbg_values = (const u8 *)edev->firmware + 1337296; + dbg_values = (const u8 *)edev->firmware + sizeof(u32); for_each_hwfn(edev, i) { qed_dbg_set_bin_ptr(&edev->hwfns[i], dbg_values); diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c index 668821dcb..8b151e907 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -374,7 +374,7 @@ static void qede_print_adapter_info(struct rte_eth_dev *dev) DP_INFO(edev, "**************************************************\n"); DP_INFO(edev, " %-20s: %s\n", "DPDK version", rte_version()); DP_INFO(edev, " %-20s: %s %c%d\n", "Chip details", - ECORE_IS_BB(edev) ? "BB" : "AH", + ECORE_IS_E5(edev) ? "AHP" : ECORE_IS_BB(edev) ? "BB" : "AH", 'A' + edev->chip_rev, (int)edev->chip_metal); snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s", @@ -2811,6 +2811,9 @@ static const struct rte_pci_id pci_id_qedevf_map[] = { { QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV) }, + { + QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_E5_IOV) + }, {.vendor_id = 0,} }; @@ -2846,6 +2849,9 @@ static const struct rte_pci_id pci_id_qede_map[] = { { QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G) }, + { + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_E5) + }, {.vendor_id = 0,} }; diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h index da4b87f5e..d065069a9 100644 --- a/drivers/net/qede/qede_ethdev.h +++ b/drivers/net/qede/qede_ethdev.h @@ -45,9 +45,9 @@ /* Driver versions */ #define QEDE_PMD_DRV_VER_STR_SIZE NAME_SIZE /* 128 */ #define QEDE_PMD_VER_PREFIX "QEDE PMD" -#define QEDE_PMD_VERSION_MAJOR 2 -#define QEDE_PMD_VERSION_MINOR 11 -#define QEDE_PMD_VERSION_REVISION 3 +#define QEDE_PMD_VERSION_MAJOR 3 +#define QEDE_PMD_VERSION_MINOR 0 +#define QEDE_PMD_VERSION_REVISION 0 #define QEDE_PMD_VERSION_PATCH 1 #define QEDE_PMD_DRV_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "." \ @@ -109,6 +109,8 @@ #define CHIP_NUM_AH_40G 0x8072 #define CHIP_NUM_AH_25G 0x8073 #define CHIP_NUM_AH_IOV 0x8090 +#define CHIP_NUM_E5 0x8170 +#define CHIP_NUM_E5_IOV 0x8190 #define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E #define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S @@ -123,7 +125,8 @@ #define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G #define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G #define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV - +#define PCI_DEVICE_ID_QLOGIC_E5 CHIP_NUM_E5 +#define PCI_DEVICE_ID_QLOGIC_E5_IOV CHIP_NUM_E5_IOV extern char qede_fw_file[];