From patchwork Fri Feb 5 12:43:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Slava Ovsiienko X-Patchwork-Id: 87798 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7CEEDA0524; Fri, 5 Feb 2021 13:43:23 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EC9E640682; Fri, 5 Feb 2021 13:43:22 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id D7AD54067B for ; Fri, 5 Feb 2021 13:43:20 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@nvidia.com) with SMTP; 5 Feb 2021 14:43:20 +0200 Received: from nvidia.com (pegasus11.mtr.labs.mlnx [10.210.16.104]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 115ChJHH031816; Fri, 5 Feb 2021 14:43:19 +0200 From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: rasland@nvidia.com, matan@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net Date: Fri, 5 Feb 2021 14:43:18 +0200 Message-Id: <20210205124318.18650-1-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 Subject: [dpdk-dev] [PATCH] net/mlx5: fix Tx queue size adjustment X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The inline data size alignments should be taken into account either to conform the rdma-core implementation of sending queue size calculation. Fixes: 7e14d144f2ea ("net/mlx5: fix Tx queue size created with DevX") Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_devx.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 1b1a72dd07..e4acab90c8 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -1077,15 +1077,18 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) * internally in the mlx5_calc_sq_size(), we do the same * for the queue being created with DevX at this point. */ - wqe_size = txq_data->tso_en ? txq_ctrl->max_tso_header : 0; + wqe_size = txq_data->tso_en ? + RTE_ALIGN(txq_ctrl->max_tso_header, MLX5_WSEG_SIZE) : 0; wqe_size += sizeof(struct mlx5_wqe_cseg) + sizeof(struct mlx5_wqe_eseg) + sizeof(struct mlx5_wqe_dseg); if (txq_data->inlen_send) - wqe_size = RTE_MAX(wqe_size, txq_data->inlen_send + - sizeof(struct mlx5_wqe_cseg) + - sizeof(struct mlx5_wqe_eseg)); - wqe_size = RTE_ALIGN_CEIL(wqe_size, MLX5_WQE_SIZE) / MLX5_WQE_SIZE; + wqe_size = RTE_MAX(wqe_size, sizeof(struct mlx5_wqe_cseg) + + sizeof(struct mlx5_wqe_eseg) + + RTE_ALIGN(txq_data->inlen_send + + sizeof(uint32_t), + MLX5_WSEG_SIZE)); + wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE) / MLX5_WQE_SIZE; /* Create Send Queue object with DevX. */ wqe_n = RTE_MIN((1UL << txq_data->elts_n) * wqe_size, (uint32_t)priv->sh->device_attr.max_qp_wr);