From patchwork Thu Feb 4 19:58:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 87761 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E837A0524; Thu, 4 Feb 2021 20:59:58 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A4F69240802; Thu, 4 Feb 2021 20:59:31 +0100 (CET) Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) by mails.dpdk.org (Postfix) with ESMTP id 63C542407EC for ; Thu, 4 Feb 2021 20:59:30 +0100 (CET) Received: by mail-pg1-f180.google.com with SMTP id z21so2884336pgj.4 for ; Thu, 04 Feb 2021 11:59:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8zx+A9hRf0VaJNIYhT0ZA57inJkSaD+LcVfJm98kn1o=; b=4uREDx+BapDXxA9H5ibropbiAYPUqLLcn7HzJaxrOoe8oI2SnYUeB2kMoAvMCObnRe YhnDKviMgPSnRGtUH2JmQthdHixC/Ge9vF62TYK24DgKb6WkJ88WpviUwtRMiupak7pz lsynpwDXhb9F6TDF22gP2BosiUDn0Y7/5+ag/NPqmFhmVBZe6TwM71fHuhhX8sphdD82 95gqfk+tcg8m4zz1WXDJYzAGMRRYmcoGgGDhZDiUZRpJY3ba9zW5kzRbeUoNCk7qJoBL KTTbqSAAcKZzXbBsONJmGIz5cpY7ieiLJXp9ohTRMTt9xqls/ae7o26qpCdaN92AEqaz 8qFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8zx+A9hRf0VaJNIYhT0ZA57inJkSaD+LcVfJm98kn1o=; b=bTEZseWJ4fXbDoA+KnrP2PIncKD6KgX2JZOdY20sC379f26/NrGGfiIHBVPj8G7NWk 6ov1mUa+hasDBbyWbkcBaRrSf7wjgcpQRNJXteWUGx8AZBeTEzm5Sn5n2avH0qE+RbJZ TD+ESsD2KCdwWmHAy/hyotjbmf78acEdQN72vka+tRgUv0X9tmgbQca5yeE6ySk6QZCl tcknq6ct3k6LzNgFMTJOE9sEc+hIPp9fB5mkSS3xSxGkJ3bzydPfwkfBNlQ4Qst/HTjh +FJGUD1SlU5ewoBA9Zu+jfLybh0TMtDwfdrEkz0v9BPXhXSexmhWnpsPwOaeRJ84kit7 cIQA== X-Gm-Message-State: AOAM5327qz6bdO9+n6epipEbW0wIbeT1aEjVbEyz716FEJpYBJWppFH/ ilSPoXbib+MG4/EW0SL/5gT1eOEAyKUfJA== X-Google-Smtp-Source: ABdhPJxGZLgVv18s5curoTygM31oJ48jSkvClXm8mOAUgGvOn7IrwlFaf7HVsBmuopEtedWpTQCUZA== X-Received: by 2002:a62:e807:0:b029:1cd:405d:f01f with SMTP id c7-20020a62e8070000b02901cd405df01fmr1082742pfi.74.1612468769287; Thu, 04 Feb 2021 11:59:29 -0800 (PST) Received: from driver-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id r14sm7757915pgi.27.2021.02.04.11.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Feb 2021 11:59:28 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer Date: Thu, 4 Feb 2021 11:58:45 -0800 Message-Id: <20210204195853.13411-7-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210204195853.13411-1-aboyer@pensando.io> References: <20210204195853.13411-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 06/14] net/ionic: cut down queue structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This will conserve resources. Rename ionic_qcq_alloc() arg from 'base' to 'type_name' for clarity. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_dev.c | 14 +++------- drivers/net/ionic/ionic_dev.h | 34 ++++++++++------------- drivers/net/ionic/ionic_lif.c | 49 ++++++++++++++++++++++------------ drivers/net/ionic/ionic_main.c | 4 +-- drivers/net/ionic/ionic_rxtx.c | 8 +++--- 5 files changed, 56 insertions(+), 53 deletions(-) diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c index 97fb8acf9b..cfaf4abc23 100644 --- a/drivers/net/ionic/ionic_dev.c +++ b/drivers/net/ionic/ionic_dev.c @@ -405,26 +405,20 @@ ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do, } int -ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, - struct ionic_queue *q, uint32_t index, uint32_t num_descs, - size_t desc_size, size_t sg_desc_size) +ionic_q_init(struct ionic_queue *q, uint32_t index, uint16_t num_descs) { uint32_t ring_size; - if (desc_size == 0 || !rte_is_power_of_2(num_descs)) + if (!rte_is_power_of_2(num_descs)) return -EINVAL; ring_size = rte_log2_u32(num_descs); - if (ring_size < 2 || ring_size > 16) return -EINVAL; - q->lif = lif; - q->idev = idev; q->index = index; q->num_descs = num_descs; - q->desc_size = desc_size; - q->sg_desc_size = sg_desc_size; + q->size_mask = num_descs - 1; q->head_idx = 0; q->tail_idx = 0; @@ -450,7 +444,7 @@ ionic_q_post(struct ionic_queue *q, bool ring_doorbell, void *cb_arg) { q->info[q->head_idx] = cb_arg; - q->head_idx = (q->head_idx + 1) & (q->num_descs - 1); + q->head_idx = Q_NEXT_TO_POST(q, 1); if (ring_doorbell) ionic_q_flush(q); diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h index 511d0bc7aa..0d1aff776b 100644 --- a/drivers/net/ionic/ionic_dev.h +++ b/drivers/net/ionic/ionic_dev.h @@ -136,25 +136,21 @@ struct ionic_dev { #define IONIC_INFO_PTR(_q, _i) (&(_q)->info[IONIC_INFO_IDX((_q), _i)]) struct ionic_queue { - struct ionic_dev *idev; - struct ionic_lif *lif; - uint32_t index; - uint32_t type; - uint32_t hw_index; - uint32_t hw_type; + uint16_t num_descs; + uint16_t head_idx; + uint16_t tail_idx; + uint16_t size_mask; + uint8_t type; + uint8_t hw_type; void *base; void *sg_base; + struct ionic_doorbell __iomem *db; void **info; + + uint32_t index; + uint32_t hw_index; rte_iova_t base_pa; rte_iova_t sg_base_pa; - uint32_t tail_idx; - uint32_t head_idx; - uint32_t num_descs; - uint32_t desc_size; - uint32_t sg_desc_size; - uint32_t qid; - uint32_t qtype; - struct ionic_doorbell __iomem *db; }; #define IONIC_INTR_NONE (-1) @@ -221,22 +217,20 @@ struct ionic_doorbell __iomem *ionic_db_map(struct ionic_lif *lif, int ionic_cq_init(struct ionic_cq *cq, uint16_t num_descs); void ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa); -typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, uint32_t cq_desc_index, +typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, uint16_t cq_desc_index, void *cb_arg); uint32_t ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do, ionic_cq_cb cb, void *cb_arg); -int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, - struct ionic_queue *q, uint32_t index, uint32_t num_descs, - size_t desc_size, size_t sg_desc_size); +int ionic_q_init(struct ionic_queue *q, uint32_t index, uint16_t num_descs); void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, void *cb_arg); -static inline uint32_t +static inline uint16_t ionic_q_space_avail(struct ionic_queue *q) { - uint32_t avail = q->tail_idx; + uint16_t avail = q->tail_idx; if (q->head_idx >= avail) avail += q->num_descs - q->head_idx - 1; diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index 462a526935..fcd6fca9a3 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -34,7 +34,7 @@ int ionic_qcq_enable(struct ionic_qcq *qcq) { struct ionic_queue *q = &qcq->q; - struct ionic_lif *lif = q->lif; + struct ionic_lif *lif = qcq->lif; struct ionic_admin_ctx ctx = { .pending_work = true, .cmd.q_control = { @@ -52,7 +52,7 @@ int ionic_qcq_disable(struct ionic_qcq *qcq) { struct ionic_queue *q = &qcq->q; - struct ionic_lif *lif = q->lif; + struct ionic_lif *lif = qcq->lif; struct ionic_admin_ctx ctx = { .pending_work = true, .cmd.q_control = { @@ -585,16 +585,17 @@ ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) } static int -ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type, +ionic_qcq_alloc(struct ionic_lif *lif, + uint8_t type, uint32_t index, - const char *base, uint32_t flags, - uint32_t num_descs, - uint32_t desc_size, - uint32_t cq_desc_size, - uint32_t sg_desc_size, + const char *type_name, + uint16_t flags, + uint16_t num_descs, + uint16_t desc_size, + uint16_t cq_desc_size, + uint16_t sg_desc_size, struct ionic_qcq **qcq) { - struct ionic_dev *idev = &lif->adapter->idev; struct ionic_qcq *new; uint32_t q_size, cq_size, sg_size, total_size; void *q_base, *cq_base, *sg_base; @@ -642,8 +643,7 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type, new->q.type = type; - err = ionic_q_init(lif, idev, &new->q, index, num_descs, - desc_size, sg_desc_size); + err = ionic_q_init(&new->q, index, num_descs); if (err) { IONIC_PRINT(ERR, "Queue initialization failed"); goto err_out_free_info; @@ -656,7 +656,7 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type, } new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev, - base /* name */, index /* queue_idx */, + type_name, index /* queue_idx */, total_size, IONIC_ALIGN, socket_id); if (!new->base_z) { @@ -727,7 +727,11 @@ ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs, int err = -ENOMEM; flags = IONIC_QCQ_F_SG; - err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags, + err = ionic_qcq_alloc(lif, + IONIC_QTYPE_RXQ, + index, + "rx", + flags, nrxq_descs, sizeof(struct ionic_rxq_desc), sizeof(struct ionic_rxq_comp), @@ -749,7 +753,11 @@ ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs, int err = -ENOMEM; flags = IONIC_QCQ_F_SG; - err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags, + err = ionic_qcq_alloc(lif, + IONIC_QTYPE_TXQ, + index, + "tx", + flags, ntxq_descs, sizeof(struct ionic_txq_desc), sizeof(struct ionic_txq_comp), @@ -770,7 +778,11 @@ ionic_admin_qcq_alloc(struct ionic_lif *lif) int err = -ENOMEM; flags = 0; - err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, + err = ionic_qcq_alloc(lif, + IONIC_QTYPE_ADMINQ, + 0, + "admin", + flags, IONIC_ADMINQ_LENGTH, sizeof(struct ionic_admin_cmd), sizeof(struct ionic_admin_comp), @@ -790,7 +802,10 @@ ionic_notify_qcq_alloc(struct ionic_lif *lif) uint32_t flags = 0; int err = -ENOMEM; - err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify", + err = ionic_qcq_alloc(lif, + IONIC_QTYPE_NOTIFYQ, + 0, + "notify", flags, IONIC_NOTIFYQ_LENGTH, sizeof(struct ionic_notifyq_cmd), @@ -1216,7 +1231,7 @@ ionic_lif_handle_fw_down(struct ionic_lif *lif) } static bool -ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg) +ionic_notifyq_cb(struct ionic_cq *cq, uint16_t cq_desc_index, void *cb_arg) { union ionic_notifyq_comp *cq_desc_base = cq->base; union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index]; diff --git a/drivers/net/ionic/ionic_main.c b/drivers/net/ionic/ionic_main.c index c9c0123d6a..b358a76f06 100644 --- a/drivers/net/ionic/ionic_main.c +++ b/drivers/net/ionic/ionic_main.c @@ -146,7 +146,7 @@ ionic_adminq_check_err(struct ionic_admin_ctx *ctx, bool timeout) } static bool -ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index, +ionic_adminq_service(struct ionic_cq *cq, uint16_t cq_desc_index, void *cb_arg __rte_unused) { struct ionic_admin_comp *cq_desc_base = cq->base; @@ -174,7 +174,7 @@ ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index, } curr_q_tail_idx = q->tail_idx; - q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); + q->tail_idx = Q_NEXT_TO_SRVC(q, 1); } while (curr_q_tail_idx != stop_index); return true; diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index 107b1cb091..ce38651559 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -98,7 +98,7 @@ ionic_tx_flush(struct ionic_qcq *txq) while (q->tail_idx != comp_index) { info = IONIC_INFO_PTR(q, q->tail_idx); - q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); + q->tail_idx = Q_NEXT_TO_SRVC(q, 1); /* Prefetch the next 4 descriptors */ if ((q->tail_idx & 0x3) == 0) @@ -540,7 +540,7 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, while (nb_tx < nb_pkts) { last = (nb_tx == (nb_pkts - 1)); - next_q_head_idx = (q->head_idx + 1) & (q->num_descs - 1); + next_q_head_idx = Q_NEXT_TO_POST(q, 1); if ((next_q_head_idx & 0x3) == 0) { struct ionic_txq_desc *desc_base = q->base; rte_prefetch0(&desc_base[next_q_head_idx]); @@ -647,7 +647,7 @@ ionic_rx_empty(struct ionic_queue *q) mbuf = info[0]; rte_mempool_put(rxq->mb_pool, mbuf); - q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); + q->tail_idx = Q_NEXT_TO_SRVC(q, 1); } } @@ -1055,7 +1055,7 @@ ionic_rxq_service(struct ionic_qcq *rxq, uint32_t work_to_do, more = (q->tail_idx != cq_desc->comp_index); curr_q_tail_idx = q->tail_idx; - q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); + q->tail_idx = Q_NEXT_TO_SRVC(q, 1); /* Prefetch the next 4 descriptors */ if ((q->tail_idx & 0x3) == 0)