diff mbox series

[v1] net/e1000: fix the invalid flow control mode setting

Message ID 20210120065337.230488-1-wenjun1.wu@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Qi Zhang
Headers show
Series [v1] net/e1000: fix the invalid flow control mode setting | expand

Checks

Context Check Description
ci/iol-testing warning Testing issues
ci/iol-mellanox-Functional success Functional Testing PASS
ci/intel-Testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/checkpatch success coding style OK

Commit Message

Wenjun Wu Jan. 20, 2021, 6:53 a.m. UTC
E1000_CTRL register should be updated according to fc_conf->mode's value.

Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org

Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
---
 drivers/net/e1000/igb_ethdev.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

Comments

Jeff Guo Jan. 20, 2021, 7:18 a.m. UTC | #1
Acked-by: Jeff Guo <jia.guo@intel.com>

> -----Original Message-----
> From: Wu, Wenjun1 <wenjun1.wu@intel.com>
> Sent: Wednesday, January 20, 2021 2:54 PM
> To: dev@dpdk.org; Guo, Jia <jia.guo@intel.com>
> Cc: Wu, Wenjun1 <wenjun1.wu@intel.com>; stable@dpdk.org
> Subject: [PATCH v1] net/e1000: fix the invalid flow control mode setting
> 
> E1000_CTRL register should be updated according to fc_conf->mode's value.
> 
> Fixes: af75078fece3 ("first public release")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
> ---
>  drivers/net/e1000/igb_ethdev.c | 34
> ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/drivers/net/e1000/igb_ethdev.c
> b/drivers/net/e1000/igb_ethdev.c index 647aa8d99..a8fc57d2c 100644
> --- a/drivers/net/e1000/igb_ethdev.c
> +++ b/drivers/net/e1000/igb_ethdev.c
> @@ -3064,6 +3064,7 @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
> struct rte_eth_fc_conf *fc_conf)
>  	uint32_t rx_buf_size;
>  	uint32_t max_high_water;
>  	uint32_t rctl;
> +	uint32_t ctrl;
> 
>  	hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
>  	if (fc_conf->autoneg != hw->mac.autoneg) @@ -3101,6 +3102,39
> @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf
> *fc_conf)
>  			rctl &= ~E1000_RCTL_PMCF;
> 
>  		E1000_WRITE_REG(hw, E1000_RCTL, rctl);
> +
> +		/*
> +		 * check if we want to change flow control mode - driver
> doesn't have native
> +		 * capability to do that, so we'll write the registers ourselves
> +		 */
> +		ctrl = E1000_READ_REG(hw, E1000_CTRL);
> +
> +		/*
> +		 * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits
> depending
> +		 * on configuration
> +		 */
> +		switch (fc_conf->mode) {
> +		case RTE_FC_NONE:
> +			ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE;
> +			break;
> +		case RTE_FC_RX_PAUSE:
> +			ctrl |= E1000_CTRL_RFCE;
> +			ctrl &= ~E1000_CTRL_TFCE;
> +			break;
> +		case RTE_FC_TX_PAUSE:
> +			ctrl |= E1000_CTRL_TFCE;
> +			ctrl &= ~E1000_CTRL_RFCE;
> +			break;
> +		case RTE_FC_FULL:
> +			ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE;
> +			break;
> +		default:
> +			PMD_INIT_LOG(ERR, "invalid flow control mode");
> +			return -EINVAL;
> +		}
> +
> +		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
> +
>  		E1000_WRITE_FLUSH(hw);
> 
>  		return 0;
> --
> 2.25.1
Zhang, Qi Z Jan. 20, 2021, 11:35 p.m. UTC | #2
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Guo, Jia
> Sent: Wednesday, January 20, 2021 3:19 PM
> To: Wu, Wenjun1 <wenjun1.wu@intel.com>; dev@dpdk.org
> Cc: stable@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH v1] net/e1000: fix the invalid flow control mode
> setting
> 
> Acked-by: Jeff Guo <jia.guo@intel.com>
> 
> > -----Original Message-----
> > From: Wu, Wenjun1 <wenjun1.wu@intel.com>
> > Sent: Wednesday, January 20, 2021 2:54 PM
> > To: dev@dpdk.org; Guo, Jia <jia.guo@intel.com>
> > Cc: Wu, Wenjun1 <wenjun1.wu@intel.com>; stable@dpdk.org
> > Subject: [PATCH v1] net/e1000: fix the invalid flow control mode
> > setting
> >
> > E1000_CTRL register should be updated according to fc_conf->mode's value.
> >
> > Fixes: af75078fece3 ("first public release")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>

Applied to dpdk-next-net-intel.

Thanks
Qi
diff mbox series

Patch

diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index 647aa8d99..a8fc57d2c 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -3064,6 +3064,7 @@  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
 	uint32_t rx_buf_size;
 	uint32_t max_high_water;
 	uint32_t rctl;
+	uint32_t ctrl;
 
 	hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 	if (fc_conf->autoneg != hw->mac.autoneg)
@@ -3101,6 +3102,39 @@  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
 			rctl &= ~E1000_RCTL_PMCF;
 
 		E1000_WRITE_REG(hw, E1000_RCTL, rctl);
+
+		/*
+		 * check if we want to change flow control mode - driver doesn't have native
+		 * capability to do that, so we'll write the registers ourselves
+		 */
+		ctrl = E1000_READ_REG(hw, E1000_CTRL);
+
+		/*
+		 * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits depending
+		 * on configuration
+		 */
+		switch (fc_conf->mode) {
+		case RTE_FC_NONE:
+			ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE;
+			break;
+		case RTE_FC_RX_PAUSE:
+			ctrl |= E1000_CTRL_RFCE;
+			ctrl &= ~E1000_CTRL_TFCE;
+			break;
+		case RTE_FC_TX_PAUSE:
+			ctrl |= E1000_CTRL_TFCE;
+			ctrl &= ~E1000_CTRL_RFCE;
+			break;
+		case RTE_FC_FULL:
+			ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE;
+			break;
+		default:
+			PMD_INIT_LOG(ERR, "invalid flow control mode");
+			return -EINVAL;
+		}
+
+		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+
 		E1000_WRITE_FLUSH(hw);
 
 		return 0;