From patchwork Mon Jan 18 20:34:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86822 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A1ACA0A03; Mon, 18 Jan 2021 21:35:46 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 39489140E3A; Mon, 18 Jan 2021 21:35:40 +0100 (CET) Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) by mails.dpdk.org (Postfix) with ESMTP id 91B8F140E2B for ; Mon, 18 Jan 2021 21:35:37 +0100 (CET) Received: by mail-pl1-f175.google.com with SMTP id y8so9249479plp.8 for ; Mon, 18 Jan 2021 12:35:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TP/jBMrmkej+4MiHfq8bnyltQIcNWdZY601enBJHyTk=; b=ExvF5ybRJ7fsOHxuz88ju/qshKBwNYAlqDt2oRDUvpnCvsVoCnQQwKVmfJzIz4IeHs X2Wd+/u1gU4hGEQwTaL18qnusa4yJ3oP7xU4qftzHJPCxdF4+Mtn6Lkekj5+M4gNNcxW aDfWnf1MNkUFcqjD5C4vsl3gyeHYg94G7xkMX1+QPdN5CWD3wDtm2aF3HkjwwygMCpEh rzjc4y4doLTwErNRVKOLu3QnN/XUWPn4lcw5HNu3ABsRobVN4RPRlP/NgABbGIk7WzXh LqMC+Tnx3yrVGgsmZfdP2q8R9X2M9jmWJi1/IxHzQVerXHmTo5XEq0QtO+xztFskTWhi F1LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TP/jBMrmkej+4MiHfq8bnyltQIcNWdZY601enBJHyTk=; b=C74Qhlh8cVMwq3NOq3mPDPU1fAIEVHAFYb5Hcm9ni0sP8yN1WDWpISdACtDegTS1+1 anoGblG7B+SomRbLL0bG70SBRP/gEHGNmfR+EnZFbhi2TNcDg5hRVg3Aohj35NG9o5te tJFcpFSZvBBs7FIEFkp21AOHAgN13FA81R+hI7rcGYjk33bjA9DojDVVZihtKXIq2WC0 7QIr0YDt2k9gj9AfW7c1nmZkKcAWQgk4B1qvsHU6atAd4IMLg/NPNXgxAKz1TqQRM+SZ K/79lhEBsWkGGhfIgibZmuj9LPkoS9NfJb3lRCwephK3O/kvjKY4waey+3wxKjWUs+UM eJeA== X-Gm-Message-State: AOAM532R4GkUXdgGDgqEOLRBFcPQG8vwIf+/aP0KtWTdvb3PKcyXQPIA wXQbZO97FHyLLaMQEuNojE9vXaUl12f2fA== X-Google-Smtp-Source: ABdhPJxKbbFNd8n0x2COph6O2dey7am2HYbkxCshVNMP6kLV2JjWgQB1YD89kRtS6HIJhMfvdWhKZQ== X-Received: by 2002:a17:90b:370d:: with SMTP id mg13mr1138320pjb.161.1611002136498; Mon, 18 Jan 2021 12:35:36 -0800 (PST) Received: from driver-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id g201sm795160pfb.81.2021.01.18.12.35.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 12:35:36 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer Date: Mon, 18 Jan 2021 12:34:57 -0800 Message-Id: <20210118203508.1332-3-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 02/13] net/ionic: observe endianness in firmware commands X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The IONIC firmware is little-endian. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_dev.c | 27 +++--- drivers/net/ionic/ionic_ethdev.c | 27 +++--- drivers/net/ionic/ionic_lif.c | 138 ++++++++++++++++--------------- drivers/net/ionic/ionic_main.c | 6 +- 4 files changed, 109 insertions(+), 89 deletions(-) diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c index 3507d4166f..c3016b2d50 100644 --- a/drivers/net/ionic/ionic_dev.c +++ b/drivers/net/ionic/ionic_dev.c @@ -165,7 +165,7 @@ ionic_dev_cmd_port_init(struct ionic_dev *idev) union ionic_dev_cmd cmd = { .port_init.opcode = IONIC_CMD_PORT_INIT, .port_init.index = 0, - .port_init.info_pa = idev->port_info_pa, + .port_init.info_pa = rte_cpu_to_le_64(idev->port_info_pa), }; ionic_dev_cmd_go(idev, &cmd); @@ -202,7 +202,7 @@ ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed) .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, .port_setattr.index = 0, .port_setattr.attr = IONIC_PORT_ATTR_SPEED, - .port_setattr.speed = speed, + .port_setattr.speed = rte_cpu_to_le_32(speed), }; ionic_dev_cmd_go(idev, &cmd); @@ -215,7 +215,7 @@ ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu) .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, .port_setattr.index = 0, .port_setattr.attr = IONIC_PORT_ATTR_MTU, - .port_setattr.mtu = mtu, + .port_setattr.mtu = rte_cpu_to_le_32(mtu), }; ionic_dev_cmd_go(idev, &cmd); @@ -292,7 +292,7 @@ ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t info_pa) { union ionic_dev_cmd cmd = { .lif_init.opcode = IONIC_CMD_LIF_INIT, - .lif_init.info_pa = info_pa, + .lif_init.info_pa = rte_cpu_to_le_64(info_pa), }; ionic_dev_cmd_go(idev, &cmd); @@ -331,12 +331,12 @@ ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq) union ionic_dev_cmd cmd = { .q_init.opcode = IONIC_CMD_Q_INIT, .q_init.type = q->type, - .q_init.index = q->index, - .q_init.flags = IONIC_QINIT_F_ENA, - .q_init.intr_index = IONIC_INTR_NONE, + .q_init.index = rte_cpu_to_le_32(q->index), + .q_init.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA), + .q_init.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), .q_init.ring_size = rte_log2_u32(q->num_descs), - .q_init.ring_base = q->base_pa, - .q_init.cq_ring_base = cq->base_pa, + .q_init.ring_base = rte_cpu_to_le_64(q->base_pa), + .q_init.cq_ring_base = rte_cpu_to_le_64(cq->base_pa), }; IONIC_PRINT(DEBUG, "adminq.q_init.ver %u", cmd.q_init.ver); @@ -517,9 +517,14 @@ ionic_adminq_cb(struct ionic_queue *q, struct ionic_admin_ctx *ctx = cb_arg; struct ionic_admin_comp *cq_desc_base = q->bound_cq->base; struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index]; + uint16_t comp_index; - if (unlikely(cq_desc->comp_index != q_desc_index)) { - IONIC_WARN_ON(cq_desc->comp_index != q_desc_index); + if (!ctx) + return; + + comp_index = rte_le_to_cpu_16(cq_desc->comp_index); + if (unlikely(comp_index != q_desc_index)) { + IONIC_WARN_ON(comp_index != q_desc_index); return; } diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c index 2face7c635..a5b2301e46 100644 --- a/drivers/net/ionic/ionic_ethdev.c +++ b/drivers/net/ionic/ionic_ethdev.c @@ -374,13 +374,15 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev, struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); struct ionic_adapter *adapter = lif->adapter; struct ionic_identity *ident = &adapter->ident; + union ionic_lif_config *cfg = &ident->lif.eth.config; IONIC_PRINT_CALL(); dev_info->max_rx_queues = (uint16_t) - ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); dev_info->max_tx_queues = (uint16_t) - ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); + /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; @@ -389,7 +391,7 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev, dev_info->max_mtu = IONIC_MAX_MTU; dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; - dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz; + dev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; dev_info->speed_capa = @@ -534,6 +536,7 @@ ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, struct ionic_adapter *adapter = lif->adapter; struct ionic_identity *ident = &adapter->ident; uint32_t i, j, index, num; + uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); IONIC_PRINT_CALL(); @@ -543,15 +546,15 @@ ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, return -EINVAL; } - if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { + if (reta_size != tbl_sz) { IONIC_PRINT(ERR, "The size of hash lookup table configured " "(%d) does not match the number hardware can support " "(%d)", - reta_size, ident->lif.eth.rss_ind_tbl_sz); + reta_size, tbl_sz); return -EINVAL; } - num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE; + num = tbl_sz / RTE_RETA_GROUP_SIZE; for (i = 0; i < num; i++) { for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { @@ -574,14 +577,15 @@ ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, struct ionic_adapter *adapter = lif->adapter; struct ionic_identity *ident = &adapter->ident; int i, num; + uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); IONIC_PRINT_CALL(); - if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { + if (reta_size != tbl_sz) { IONIC_PRINT(ERR, "The size of hash lookup table configured " "(%d) does not match the number hardware can support " "(%d)", - reta_size, ident->lif.eth.rss_ind_tbl_sz); + reta_size, tbl_sz); return -EINVAL; } @@ -1228,11 +1232,12 @@ eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, goto err_free_adapter; } - adapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters; + adapter->max_mac_addrs = + rte_le_to_cpu_32(adapter->ident.lif.eth.max_ucast_filters); - if (adapter->ident.dev.nlifs != 1) { + if (rte_le_to_cpu_32(adapter->ident.dev.nlifs) != 1) { IONIC_PRINT(ERR, "Unexpected request for %d LIFs", - adapter->ident.dev.nlifs); + rte_le_to_cpu_32(adapter->ident.dev.nlifs)); goto err_free_adapter; } diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index 856e977186..15e291b604 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -25,7 +25,7 @@ ionic_qcq_enable(struct ionic_qcq *qcq) .cmd.q_control = { .opcode = IONIC_CMD_Q_CONTROL, .type = q->type, - .index = q->index, + .index = rte_cpu_to_le_32(q->index), .oper = IONIC_Q_ENABLE, }, }; @@ -43,7 +43,7 @@ ionic_qcq_disable(struct ionic_qcq *qcq) .cmd.q_control = { .opcode = IONIC_CMD_Q_CONTROL, .type = q->type, - .index = q->index, + .index = rte_cpu_to_le_32(q->index), .oper = IONIC_Q_DISABLE, }, }; @@ -241,7 +241,7 @@ ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr) .pending_work = true, .cmd.rx_filter_add = { .opcode = IONIC_CMD_RX_FILTER_ADD, - .match = IONIC_RX_FILTER_MATCH_MAC, + .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC), }, }; int err; @@ -253,7 +253,7 @@ ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr) return err; IONIC_PRINT(INFO, "rx_filter add (id %d)", - ctx.comp.rx_filter_add.filter_id); + rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); } @@ -280,7 +280,7 @@ ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr) return -ENOENT; } - ctx.cmd.rx_filter_del.filter_id = f->filter_id; + ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); ionic_rx_filter_free(f); rte_spinlock_unlock(&lif->rx_filters.lock); @@ -290,7 +290,7 @@ ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr) return err; IONIC_PRINT(INFO, "rx_filter del (id %d)", - ctx.cmd.rx_filter_del.filter_id); + rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); return 0; } @@ -364,8 +364,8 @@ ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid) .pending_work = true, .cmd.rx_filter_add = { .opcode = IONIC_CMD_RX_FILTER_ADD, - .match = IONIC_RX_FILTER_MATCH_VLAN, - .vlan.vlan = vid, + .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN), + .vlan.vlan = rte_cpu_to_le_16(vid), }, }; int err; @@ -375,7 +375,7 @@ ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid) return err; IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid, - ctx.comp.rx_filter_add.filter_id); + rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); } @@ -402,7 +402,7 @@ ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid) return -ENOENT; } - ctx.cmd.rx_filter_del.filter_id = f->filter_id; + ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); ionic_rx_filter_free(f); rte_spinlock_unlock(&lif->rx_filters.lock); @@ -411,7 +411,7 @@ ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid) return err; IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid, - ctx.cmd.rx_filter_del.filter_id); + rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); return 0; } @@ -438,7 +438,7 @@ ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode) .pending_work = true, .cmd.rx_mode_set = { .opcode = IONIC_CMD_RX_MODE_SET, - .rx_mode = rx_mode, + .rx_mode = rte_cpu_to_le_16(rx_mode), }, }; int err; @@ -530,7 +530,7 @@ ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu) .cmd.lif_setattr = { .opcode = IONIC_CMD_LIF_SETATTR, .attr = IONIC_LIF_ATTR_MTU, - .mtu = new_mtu, + .mtu = rte_cpu_to_le_32(new_mtu), }, }; int err; @@ -942,16 +942,19 @@ int ionic_lif_rss_config(struct ionic_lif *lif, const uint16_t types, const uint8_t *key, const uint32_t *indir) { + struct ionic_adapter *adapter = lif->adapter; struct ionic_admin_ctx ctx = { .pending_work = true, .cmd.lif_setattr = { .opcode = IONIC_CMD_LIF_SETATTR, .attr = IONIC_LIF_ATTR_RSS, - .rss.types = types, - .rss.addr = lif->rss_ind_tbl_pa, + .rss.types = rte_cpu_to_le_16(types), + .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa), }, }; unsigned int i; + uint16_t tbl_sz = + rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); IONIC_PRINT_CALL(); @@ -961,7 +964,7 @@ ionic_lif_rss_config(struct ionic_lif *lif, memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); if (indir) - for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++) + for (i = 0; i < tbl_sz; i++) lif->rss_ind_tbl[i] = indir[i]; memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, @@ -973,6 +976,7 @@ ionic_lif_rss_config(struct ionic_lif *lif, static int ionic_lif_rss_setup(struct ionic_lif *lif) { + struct ionic_adapter *adapter = lif->adapter; static const uint8_t toeplitz_symmetric_key[] = { 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, @@ -981,7 +985,8 @@ ionic_lif_rss_setup(struct ionic_lif *lif) 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, }; uint32_t i; - uint16_t tbl_sz = lif->adapter->ident.lif.eth.rss_ind_tbl_sz; + uint16_t tbl_sz = + rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); IONIC_PRINT_CALL(); @@ -1107,7 +1112,8 @@ ionic_link_status_check(struct ionic_lif *lif) return; if (link_up) { - adapter->link_speed = lif->info->status.link_speed; + adapter->link_speed = + rte_le_to_cpu_32(lif->info->status.link_speed); IONIC_PRINT(DEBUG, "Link up - %d Gbps", adapter->link_speed); } else { @@ -1230,7 +1236,7 @@ ionic_lif_adminq_init(struct ionic_lif *lif) ionic_dev_cmd_comp(idev, &comp); q->hw_type = comp.hw_type; - q->hw_index = comp.hw_index; + q->hw_index = rte_le_to_cpu_32(comp.hw_index); q->db = ionic_db_map(lif, q); IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type); @@ -1255,18 +1261,17 @@ ionic_lif_notifyq_init(struct ionic_lif *lif) .cmd.q_init = { .opcode = IONIC_CMD_Q_INIT, .type = q->type, - .index = q->index, - .flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA), - .intr_index = qcq->intr.index, + .index = rte_cpu_to_le_32(q->index), + .intr_index = rte_cpu_to_le_16(qcq->intr.index), + .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ | + IONIC_QINIT_F_ENA), .ring_size = rte_log2_u32(q->num_descs), - .ring_base = q->base_pa, + .ring_base = rte_cpu_to_le_64(q->base_pa), } }; - IONIC_PRINT(DEBUG, "notifyq_init.index %d", - ctx.cmd.q_init.index); - IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", - ctx.cmd.q_init.ring_base); + IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index); + IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa); IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d", ctx.cmd.q_init.ring_size); IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver); @@ -1276,7 +1281,7 @@ ionic_lif_notifyq_init(struct ionic_lif *lif) return err; q->hw_type = ctx.comp.q_init.hw_type; - q->hw_index = ctx.comp.q_init.hw_index; + q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); q->db = NULL; IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type); @@ -1299,7 +1304,7 @@ ionic_lif_set_features(struct ionic_lif *lif) .cmd.lif_setattr = { .opcode = IONIC_CMD_LIF_SETATTR, .attr = IONIC_LIF_ATTR_FEATURES, - .features = lif->features, + .features = rte_cpu_to_le_64(lif->features), }, }; int err; @@ -1308,8 +1313,8 @@ ionic_lif_set_features(struct ionic_lif *lif) if (err) return err; - lif->hw_features = (ctx.cmd.lif_setattr.features & - ctx.comp.lif_setattr.features); + lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features & + ctx.comp.lif_setattr.features); if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG"); @@ -1360,20 +1365,20 @@ ionic_lif_txq_init(struct ionic_qcq *qcq) .cmd.q_init = { .opcode = IONIC_CMD_Q_INIT, .type = q->type, - .index = q->index, - .flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA, - .intr_index = IONIC_INTR_NONE, + .index = rte_cpu_to_le_32(q->index), + .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | + IONIC_QINIT_F_ENA), + .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), .ring_size = rte_log2_u32(q->num_descs), - .ring_base = q->base_pa, - .cq_ring_base = cq->base_pa, - .sg_ring_base = q->sg_base_pa, + .ring_base = rte_cpu_to_le_64(q->base_pa), + .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), + .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), }, }; int err; - IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index); - IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", - ctx.cmd.q_init.ring_base); + IONIC_PRINT(DEBUG, "txq_init.index %d", q->index); + IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa); IONIC_PRINT(DEBUG, "txq_init.ring_size %d", ctx.cmd.q_init.ring_size); IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver); @@ -1383,7 +1388,7 @@ ionic_lif_txq_init(struct ionic_qcq *qcq) return err; q->hw_type = ctx.comp.q_init.hw_type; - q->hw_index = ctx.comp.q_init.hw_index; + q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); q->db = ionic_db_map(lif, q); IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type); @@ -1406,20 +1411,20 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq) .cmd.q_init = { .opcode = IONIC_CMD_Q_INIT, .type = q->type, - .index = q->index, - .flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA, - .intr_index = IONIC_INTR_NONE, + .index = rte_cpu_to_le_32(q->index), + .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | + IONIC_QINIT_F_ENA), + .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), .ring_size = rte_log2_u32(q->num_descs), - .ring_base = q->base_pa, - .cq_ring_base = cq->base_pa, - .sg_ring_base = q->sg_base_pa, + .ring_base = rte_cpu_to_le_64(q->base_pa), + .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), + .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), }, }; int err; - IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index); - IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", - ctx.cmd.q_init.ring_base); + IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index); + IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa); IONIC_PRINT(DEBUG, "rxq_init.ring_size %d", ctx.cmd.q_init.ring_size); IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver); @@ -1429,7 +1434,7 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq) return err; q->hw_type = ctx.comp.q_init.hw_type; - q->hw_index = ctx.comp.q_init.hw_index; + q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); q->db = ionic_db_map(lif, q); qcq->flags |= IONIC_QCQ_F_INITED; @@ -1496,7 +1501,7 @@ ionic_lif_init(struct ionic_lif *lif) if (err) return err; - lif->hw_index = comp.hw_index; + lif->hw_index = rte_cpu_to_le_16(comp.hw_index); err = ionic_lif_adminq_init(lif); if (err) @@ -1582,10 +1587,11 @@ ionic_lif_configure(struct ionic_lif *lif) struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode; struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode; struct ionic_identity *ident = &lif->adapter->ident; + union ionic_lif_config *cfg = &ident->lif.eth.config; uint32_t ntxqs_per_lif = - ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); uint32_t nrxqs_per_lif = - ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues; uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues; @@ -1722,6 +1728,7 @@ ionic_lif_identify(struct ionic_adapter *adapter) { struct ionic_dev *idev = &adapter->idev; struct ionic_identity *ident = &adapter->ident; + union ionic_lif_config *cfg = &ident->lif.eth.config; int err; unsigned int i; unsigned int lif_words = sizeof(ident->lif.words) / @@ -1741,23 +1748,23 @@ ionic_lif_identify(struct ionic_adapter *adapter) ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]); IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ", - ident->lif.capabilities); + rte_le_to_cpu_64(ident->lif.capabilities)); IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ", - ident->lif.eth.max_ucast_filters); + rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters)); IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ", - ident->lif.eth.max_mcast_filters); + rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters)); IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ", - ident->lif.eth.config.features); + rte_le_to_cpu_64(cfg->features)); IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ", - ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]); + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ])); IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ", - ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]); + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ])); IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ", - ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]); + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ])); IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ", - ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]); + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ])); return 0; } @@ -1766,12 +1773,13 @@ int ionic_lifs_size(struct ionic_adapter *adapter) { struct ionic_identity *ident = &adapter->ident; - uint32_t nintrs, dev_nintrs = ident->dev.nintrs; + union ionic_lif_config *cfg = &ident->lif.eth.config; + uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs); adapter->max_ntxqs_per_lif = - ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); adapter->max_nrxqs_per_lif = - ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); nintrs = 1 /* notifyq */; diff --git a/drivers/net/ionic/ionic_main.c b/drivers/net/ionic/ionic_main.c index 467696a546..3f15a6f2f2 100644 --- a/drivers/net/ionic/ionic_main.c +++ b/drivers/net/ionic/ionic_main.c @@ -340,8 +340,10 @@ ionic_port_identify(struct ionic_adapter *adapter) ioread32(&idev->dev_cmd->data[i]); } - IONIC_PRINT(INFO, "speed %d", ident->port.config.speed); - IONIC_PRINT(INFO, "mtu %d", ident->port.config.mtu); + IONIC_PRINT(INFO, "speed %d", + rte_le_to_cpu_32(ident->port.config.speed)); + IONIC_PRINT(INFO, "mtu %d", + rte_le_to_cpu_32(ident->port.config.mtu)); IONIC_PRINT(INFO, "state %d", ident->port.config.state); IONIC_PRINT(INFO, "an_enable %d", ident->port.config.an_enable); IONIC_PRINT(INFO, "fec_type %d", ident->port.config.fec_type);