From patchwork Fri Jan 15 07:00:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhang X-Patchwork-Id: 86656 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 960E9A0A02; Fri, 15 Jan 2021 08:00:43 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 31621140D4B; Fri, 15 Jan 2021 08:00:43 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id B19A4140D36; Fri, 15 Jan 2021 08:00:40 +0100 (CET) IronPort-SDR: pgOSxYm9aNgaNSHCwl1RFV0m6mY+R0gwMprpBz5JaexeCFgNxaA6CJkPc/vVIMwt651nN/BCNg WoWInJu9XXWA== X-IronPort-AV: E=McAfee;i="6000,8403,9864"; a="242578347" X-IronPort-AV: E=Sophos;i="5.79,348,1602572400"; d="scan'208";a="242578347" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2021 23:00:37 -0800 IronPort-SDR: Rz7lAjIolHtkXxXJeWU33rP/ux/yUgEH/2D1OH1necbALY/3Cz3xj/BJHAMdSP2hXeQabXfV0b 6NjS6f4TcsPA== X-IronPort-AV: E=Sophos;i="5.79,348,1602572400"; d="scan'208";a="401196534" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2021 23:00:34 -0800 From: "Zhang,Alvin" To: jia.guo@intel.com, haiyue.wang@intel.com, WeiX.Xie@intel.com Cc: dev@dpdk.org, Alvin Zhang , stable@dpdk.org Date: Fri, 15 Jan 2021 15:00:29 +0800 Message-Id: <20210115070029.2768-1-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20210115023126.26248-1-alvinx.zhang@intel.com> References: <20210115023126.26248-1-alvinx.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3] net/ixgbe: fix configuration of max frame size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Alvin Zhang For 82599 NIC, jumbo frame feature is not supported in IOV mode, but if a VF requests to configure the frame size to that not bigger than RTE_ETHER_MAX_LEN, the PMD should not return -1. This patch keeps ixgbe PMD's handling mode consistent with kernel driver in above situation. In addition, the value set by the command IXGBE_VF_SET_LPE represents the max frame size, not the mtu. Fixes: 1b9ea09c067b ("ixgbe: support X550") Fixes: 95a27b3ba5f5 ("net/ixgbe: enable jumbo frame for VF") Cc: stable@dpdk.org Signed-off-by: Alvin Zhang Tested-by: Xie,WeiX < weix.xie@intel.com> --- V3: Restore variable name from cur_frame_size to max_frs. --- drivers/net/ixgbe/ixgbe_pf.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_pf.c b/drivers/net/ixgbe/ixgbe_pf.c index 833863a..1ffde56 100644 --- a/drivers/net/ixgbe/ixgbe_pf.c +++ b/drivers/net/ixgbe/ixgbe_pf.c @@ -555,17 +555,20 @@ int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev) ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf) { struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint32_t new_mtu = msgbuf[1]; + uint32_t max_frame = msgbuf[1]; uint32_t max_frs; uint32_t hlreg0; - int max_frame = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; /* X540 and X550 support jumbo frames in IOV mode */ if (hw->mac.type != ixgbe_mac_X540 && hw->mac.type != ixgbe_mac_X550 && hw->mac.type != ixgbe_mac_X550EM_x && - hw->mac.type != ixgbe_mac_X550EM_a) - return -1; + hw->mac.type != ixgbe_mac_X550EM_a) { + if (max_frame > dev->data->dev_conf.rxmode.max_rx_pkt_len) + return -1; + + return 0; + } if (max_frame < RTE_ETHER_MIN_LEN || max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) @@ -573,9 +576,9 @@ int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev) max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) & IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT; - if (max_frs < new_mtu) { + if (max_frs < max_frame) { hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); - if (new_mtu > RTE_ETHER_MAX_LEN) { + if (max_frame > RTE_ETHER_MAX_LEN) { dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; hlreg0 |= IXGBE_HLREG0_JUMBOEN; @@ -586,7 +589,7 @@ int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev) } IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); - max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT; + max_frs = max_frame << IXGBE_MHADD_MFS_SHIFT; IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs); }