From patchwork Mon Jan 11 17:43:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 86329 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 13735A09FF; Mon, 11 Jan 2021 18:44:32 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CACD4140FAE; Mon, 11 Jan 2021 18:44:15 +0100 (CET) Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) by mails.dpdk.org (Postfix) with ESMTP id 0FF17140F9F for ; Mon, 11 Jan 2021 18:44:12 +0100 (CET) Received: by mail-pl1-f174.google.com with SMTP id s15so208400plr.9 for ; Mon, 11 Jan 2021 09:44:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7CF7wjFeCjl7zOahbAJm+gVEu5lGZ3LdjcDXoVa4RKk=; b=PxtJD7I3z/iz6REVP73kBwVtuJsS8KAY46Y572ZmZMs0xGql47nPqvVFS0QvwAp2fy L4olGyohA0jVngdL4nxaOneVeuGzwb625rY5JadcjNuiD3h+QQsnecXO8dptEB+sgTmT spBL1hUpu8kFonX6z0v9yhmM+KvCUhvJ2N3z4ckSbzmpuRDyj8K/CQvbKDU0kFqDbbMf 692vwj8AoOvbGOyuD4KU78Og6bH2dh9MIg5JmkR3W9mGH0fpOmkv7ssbiWZo1VR+RqVF jYxsTHq8R042TgmoXnB7pSMl35qxdqEbPFi07C3+fdaFhQ/wbpvy17Y4gSZ3oP0HDYDW Eqwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7CF7wjFeCjl7zOahbAJm+gVEu5lGZ3LdjcDXoVa4RKk=; b=RB9cKgiXKMBC15nLlQayypdmJ+sVHr+E5HFZ3Pc4UR+Gi+LxTsr7aFtKd7dcNT5SFw gqe246KKRHlveBPrnhfYd5NnutDsRxzn2C98ZEngm2Bw88OxU4x+EkoUAxkmaiQQQhwI 4k2ID0fNJ724HgOlBm9yfAO2cZgR0PkuIGNeWrKHo0A6hSUrO9Ue6yvdb2YnHysraSP5 q3AfixhZFSLcF/m0FTqyXc8Dyo3V52nmLhouKeI8p56QJgrtHM33dq4DRD7JSQNm8hCz X68MC8uhyVr09US/xvMlXKjkn/m9ieWP1yCUEbl0l5byYyfJQPwdjn61fiCiOPzC3nbc wPDA== X-Gm-Message-State: AOAM531z5PhD+ND6HT6XA9BYqvG1CzTHLke+Axb83O7fOknGVSRdwW/x +meI2KlXPQV0JMqlrgSCiFj/bK7/E8wxQw== X-Google-Smtp-Source: ABdhPJzAhr6DKezx8cIehcsU7MGwPdX/BAf8885eZhJGL2XXNHZb5lpHuZ0ufR5RnkN4OGrHP3Xnvg== X-Received: by 2002:a17:90a:f40e:: with SMTP id ch14mr390049pjb.172.1610387050905; Mon, 11 Jan 2021 09:44:10 -0800 (PST) Received: from localhost.localdomain ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id t6sm4750pjg.49.2021.01.11.09.44.09 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jan 2021 09:44:10 -0800 (PST) From: Ajit Khaparde X-Google-Original-From: Ajit Khaparde To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Kalesh AP Date: Mon, 11 Jan 2021 09:43:57 -0800 Message-Id: <20210111174400.10606-4-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20210111174400.10606-1-ajit.khaparde@broadcom.com> References: <20210108051301.33416-1-ajit.khaparde@broadcom.com> <20210111174400.10606-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 3/6] net/bnxt: modify VNIC accounting X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP Modify VNIC accounting when enabling RFS on newer chips. Unlike legacy chips, newer chips don't need additional VNIC resources for ntuple filter. Fix the code accordingly so that we don't reserve and allocate additional VNICs on newer chips. Signed-off-by: Kalesh AP Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt.h | 3 +++ drivers/net/bnxt/bnxt_ethdev.c | 18 ++++++++++++++---- drivers/net/bnxt/bnxt_flow.c | 14 ++++++++++++-- drivers/net/bnxt/bnxt_hwrm.c | 32 ++++++++++++++++++++++++++++++++ drivers/net/bnxt/bnxt_hwrm.h | 5 +++-- 5 files changed, 64 insertions(+), 8 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 14f52b2c4..276d807c7 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -643,6 +643,9 @@ struct bnxt { #define BNXT_FLAG_DFLT_MAC_SET BIT(26) #define BNXT_FLAG_TRUFLOW_EN BIT(27) #define BNXT_FLAG_GFID_ENABLE BIT(28) +#define BNXT_FLAG_RFS_NEEDS_VNIC BIT(29) +#define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(30) +#define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC) #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 02ab87bba..8ca4fb151 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -748,11 +748,17 @@ static int bnxt_init_chip(struct bnxt *bp) goto err_out; } + /* default vnic 0 */ + rc = bnxt_setup_one_vnic(bp, 0); + if (rc) + goto err_out; /* VNIC configuration */ - for (i = 0; i < bp->nr_vnics; i++) { - rc = bnxt_setup_one_vnic(bp, i); - if (rc) - goto err_out; + if (BNXT_RFS_NEEDS_VNIC(bp)) { + for (i = 1; i < bp->nr_vnics; i++) { + rc = bnxt_setup_one_vnic(bp, i); + if (rc) + goto err_out; + } } rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); @@ -4698,6 +4704,10 @@ static int bnxt_init_fw(struct bnxt *bp) if (rc) return rc; + rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); + if (rc) + return rc; + bnxt_hwrm_port_mac_qcfg(bp); bnxt_hwrm_parent_pf_qcfg(bp); diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c index 127d51c45..07d359edf 100644 --- a/drivers/net/bnxt/bnxt_flow.c +++ b/drivers/net/bnxt/bnxt_flow.c @@ -1056,6 +1056,13 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev, } PMD_DRV_LOG(DEBUG, "Queue index %d\n", act_q->index); + if (use_ntuple && !BNXT_RFS_NEEDS_VNIC(bp)) { + filter->flags = + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX; + filter->dst_id = act_q->index; + goto skip_vnic_alloc; + } + vnic_id = attr->group; if (!vnic_id) { PMD_DRV_LOG(DEBUG, "Group id is 0\n"); @@ -1127,7 +1134,7 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev, PMD_DRV_LOG(DEBUG, "Setting vnic ff_idx %d\n", vnic->ff_pool_idx); filter->dst_id = vnic->fw_vnic_id; - +skip_vnic_alloc: /* For ntuple filter, create the L2 filter with default VNIC. * The user specified redirect queue will be set while creating * the ntuple filter in hardware. @@ -1808,7 +1815,10 @@ bnxt_flow_create(struct rte_eth_dev *dev, } } - vnic = find_matching_vnic(bp, filter); + if (BNXT_RFS_NEEDS_VNIC(bp)) + vnic = find_matching_vnic(bp, filter); + else + vnic = BNXT_GET_DEFAULT_VNIC(bp); done: if (!ret || update_flow) { flow->filter = filter; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 350fe2f97..56e2e33a9 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -5834,3 +5834,35 @@ int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp) rep_bp->vf_id); return rc; } + +int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp) +{ + struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp = + bp->hwrm_cmd_resp_addr; + struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; + uint32_t flags = 0; + int rc = 0; + + if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT)) + return 0; + + if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) { + PMD_DRV_LOG(DEBUG, + "Not a PF or trusted VF. Command not supported\n"); + return 0; + } + + HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + + HWRM_CHECK_RESULT(); + flags = rte_le_to_cpu_32(resp->flags); + HWRM_UNLOCK(); + + if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED) + bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2; + else + bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC; + + return rc; +} diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 4b3290773..7deea29ca 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -55,8 +55,8 @@ struct hwrm_func_qstats_output; #define HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK \ HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK -#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN \ -HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED +#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED \ + HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED #define HWRM_SPEC_CODE_1_8_4 0x10804 #define HWRM_SPEC_CODE_1_9_0 0x10900 @@ -300,4 +300,5 @@ int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid, uint16_t *first_vf_id); int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep); int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep); +int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp); #endif