From patchwork Sun Jan 3 03:46:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 85934 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7A9D7A09E4; Sun, 3 Jan 2021 04:46:54 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6440916069B; Sun, 3 Jan 2021 04:46:43 +0100 (CET) Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) by mails.dpdk.org (Postfix) with ESMTP id 4F579160699 for ; Sun, 3 Jan 2021 04:46:42 +0100 (CET) Received: by mail-pl1-f175.google.com with SMTP id j1so12667983pld.3 for ; Sat, 02 Jan 2021 19:46:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=mPrOA4KdIAIDs8aI0G1567hsJ2WpADEIMGOjosqBK28=; b=aS8vsc/ZkzpjewWv79TuLwEbLUtkYziLO0UGqym4U2oweMaGP2+aneCq2MW/iN3AQT +yJdEBuuPueYQUUf4B+GJBoXeVHjkrH7F3x5YzI/6AvYQL0uh6tgYtuP/boL0SkmEI01 ySnZE4svQMVOr9+Jj6nUaJ0GJD6X29zKVWSP8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=mPrOA4KdIAIDs8aI0G1567hsJ2WpADEIMGOjosqBK28=; b=BGJaXqr0y3g2Htwpq4pSy0hJ4Jwltm+4o/lLXWoXS54/xJVL/JW42qT7yK0eMqPAh9 tHS9TXjhI1unkj+5QqzBgSTwG85pbMjxoos2LLPPsSo8cRjXBzgBBXxF2gTANPjV+NvS vt/nIbi3z/kklGMvMcnnJP2CNE/ypTzm3EQV92GJKVZB8lHuw9z91e00Z43OkvIoBHup v19ZTdWF8tgdXms9LU7eGqy468U/c/IScMhNF+BGRKWNaLUQFqtY0Gyb+zj2f9xrKTR0 foCTrrtb2RSCRiZcBG9lLqfOHLeiYyx8l26ijqox013JCVwLm2GGE/GJ4BmaRMRXFetf IpyA== X-Gm-Message-State: AOAM533kAsmiKFrzoLFQCTZf1UeS19bxwPOVHxClvlFFmelZVQr1TFuG pWbM4kHXakUDUAMJFPuT3VsHS1MVYbbhoQguWyrwZIiQx5EHJMNvCPyEQUK5Cb4wJW4A7aQQqww RzQrTb/6vrYoDpRIGvC5JVLMTzdJZKSJxmu18Bg6Pkf0nDVhuqRsivrnj9MLW2UiXMw== X-Google-Smtp-Source: ABdhPJysqkv8F84CsSdcKU2cefV2mlbirIXA+MsQ+/BG+cQqEYEOy5GiNXee3mviHqc4dgax6k00TQ== X-Received: by 2002:a17:902:76c2:b029:dc:1aa4:28f1 with SMTP id j2-20020a17090276c2b02900dc1aa428f1mr67227222plt.79.1609645601112; Sat, 02 Jan 2021 19:46:41 -0800 (PST) Received: from localhost.localdomain ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id k7sm51391194pfh.201.2021.01.02.19.46.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 02 Jan 2021 19:46:40 -0800 (PST) From: Ajit Khaparde To: dev@dpdk.org Cc: Kalesh AP Date: Sat, 2 Jan 2021 19:46:23 -0800 Message-Id: <20210103034627.80169-3-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20210103034627.80169-1-ajit.khaparde@broadcom.com> References: <20201220052430.99990-1-ajit.khaparde@broadcom.com> <20210103034627.80169-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [dpdk-dev] [PATCH v2 2/6] net/bnxt: add new RX checksum mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP The 58818 chips support two different checksum modes. Host driver has to register with FW which checksum mode it prefers to use. DPDK driver want to use "cs_all_ok_mode=1". FW advertises the support of the different checksum modes on per VNIC basis in the HWRM_VNIC_QCAPS response. Driver should use HWRM_VNIC_CFG to configure the needed checksum mode. Signed-off-by: Kalesh AP Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt.h | 1 + drivers/net/bnxt/bnxt_hwrm.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 0d3998f20..14f52b2c4 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -679,6 +679,7 @@ struct bnxt { uint32_t vnic_cap_flags; #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) #define BNXT_VNIC_CAP_OUTER_RSS BIT(1) +#define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2) unsigned int rx_nr_rings; unsigned int rx_cp_nr_rings; unsigned int rx_num_qs_per_vnic; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 36c229de1..350fe2f97 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -860,6 +860,9 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP) bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS; + if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP) + bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2; + bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported); HWRM_UNLOCK(); @@ -1961,6 +1964,11 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic) rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id); enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID | HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID; + if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) { + enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE; + req.rx_csum_v2_mode = + HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK; + } goto config_mru; }