From patchwork Thu Dec 31 07:22:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pradeep Nalla X-Patchwork-Id: 85916 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3853EA0A00; Thu, 31 Dec 2020 08:23:26 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 34022140CF9; Thu, 31 Dec 2020 08:23:03 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7B01E140CE4 for ; Thu, 31 Dec 2020 08:22:58 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0BV7G5RC022206 for ; Wed, 30 Dec 2020 23:22:57 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=TZcqjor1jPSuJZ5fyRz4kyV1x/WOcBHyBvln5BnrHH8=; b=RepPiZpFQrBcCn3j3n5NxSv+0VIzD7hAs0Nyf7usARJPXyP41Hj/XO8dhBBbNCYpXGOC 3z0+uss2ghoi/7dFzV/Qb5ss3EXYOfBfjENnD9l/QEY4ykzdkBIQJjSROpBuXp88UJgi SVtiqx5ZsG5XcYRZfrbyGox4Ail4aixAlIqi0PYLhpENwRW6E710oW3yS2YfzFfj36wQ QnD6ET1qLLqhQ3CqHoqJXXoP8SpqFeuAoa7nhd70thWX7pzQqqKuf2qUQ6E2cy0Xn/1n mJipI+cfPvD4VUaRqC4DOlFC/0KnjMjp8qS2ue9wFxqaoSEPC98gjY5KOAShrvus45gw 4A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 35rqgehx54-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 30 Dec 2020 23:22:57 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Dec 2020 23:22:56 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Dec 2020 23:22:56 -0800 Received: from localhost.localdomain (unknown [10.111.145.157]) by maili.marvell.com (Postfix) with ESMTP id 227C13F7041; Wed, 30 Dec 2020 23:22:56 -0800 (PST) From: "Nalla, Pradeep" To: "Nalla, Pradeep" , Radha Mohan Chintakuntla , Veerasenareddy Burru CC: , , Date: Thu, 31 Dec 2020 07:22:37 +0000 Message-ID: <20201231072247.5719-6-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201231072247.5719-1-pnalla@marvell.com> References: <20201231072247.5719-1-pnalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-31_02:2020-12-30, 2020-12-31 signatures=0 Subject: [dpdk-dev] [PATCH 05/15] net/octeontx_ep: Add dev info get and configure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "Nalla Pradeep" Add device information get and device configure operations. Signed-off-by: Nalla Pradeep --- drivers/net/octeontx_ep/otx_ep_common.h | 15 +++++ drivers/net/octeontx_ep/otx_ep_ethdev.c | 80 +++++++++++++++++++++++++ drivers/net/octeontx_ep/otx_ep_rxtx.h | 10 ++++ 3 files changed, 105 insertions(+) create mode 100644 drivers/net/octeontx_ep/otx_ep_rxtx.h diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h index f096bec1c0..a56a68bbec 100644 --- a/drivers/net/octeontx_ep/otx_ep_common.h +++ b/drivers/net/octeontx_ep/otx_ep_common.h @@ -7,9 +7,12 @@ #define OTX_EP_MAX_RINGS_PER_VF (8) #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF #define OTX_EP_64BYTE_INSTR (64) +#define OTX_EP_MIN_IQ_DESCRIPTORS (128) +#define OTX_EP_MIN_OQ_DESCRIPTORS (128) #define OTX_EP_MAX_IQ_DESCRIPTORS (8192) #define OTX_EP_MAX_OQ_DESCRIPTORS (8192) #define OTX_EP_OQ_BUF_SIZE (2048) +#define OTX_EP_MIN_RX_BUF_SIZE (64) #define OTX_EP_OQ_INFOPTR_MODE (0) #define OTX_EP_OQ_REFIL_THRESHOLD (16) @@ -112,6 +115,10 @@ struct otx_ep_device { struct otx_ep_fn_list fn_list; + uint32_t max_tx_queues; + + uint32_t max_rx_queues; + /* SR-IOV info */ struct otx_ep_sriov_info sriov_info; @@ -119,5 +126,13 @@ struct otx_ep_device { const struct otx_ep_config *conf; int port_configured; + + uint64_t rx_offloads; + uint64_t tx_offloads; }; + +#define OTX_EP_MAX_PKT_SZ 64000U + +#define OTX_EP_MAX_MAC_ADDRS 1 + #endif /* _OTX_EP_COMMON_H_ */ diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c index 7ae9618e72..908bed1f60 100644 --- a/drivers/net/octeontx_ep/otx_ep_ethdev.c +++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c @@ -10,8 +10,56 @@ #include "otx_ep_common.h" #include "otx_ep_vf.h" #include "otx2_ep_vf.h" +#include "otx_ep_rxtx.h" #define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private) + +static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = { + .nb_max = OTX_EP_MAX_OQ_DESCRIPTORS, + .nb_min = OTX_EP_MIN_OQ_DESCRIPTORS, + .nb_align = OTX_EP_RXD_ALIGN, +}; + +static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = { + .nb_max = OTX_EP_MAX_IQ_DESCRIPTORS, + .nb_min = OTX_EP_MIN_IQ_DESCRIPTORS, + .nb_align = OTX_EP_TXD_ALIGN, +}; + +static int +otx_ep_dev_info_get(struct rte_eth_dev *eth_dev, + struct rte_eth_dev_info *devinfo) +{ + struct otx_ep_device *otx_epvf; + struct rte_pci_device *pdev; + uint32_t dev_id; + + otx_epvf = (struct otx_ep_device *)OTX_EP_DEV(eth_dev); + pdev = otx_epvf->pdev; + dev_id = pdev->id.device_id; + + devinfo->speed_capa = ETH_LINK_SPEED_10G; + devinfo->max_rx_queues = otx_epvf->max_rx_queues; + devinfo->max_tx_queues = otx_epvf->max_tx_queues; + + devinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE; + if (dev_id == PCI_DEVID_OCTEONTX_EP_VF || + dev_id == PCI_DEVID_OCTEONTX2_EP_NET_VF || + dev_id == PCI_DEVID_98XX_EP_NET_VF) { + devinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ; + devinfo->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME; + devinfo->rx_offload_capa |= DEV_RX_OFFLOAD_SCATTER; + devinfo->tx_offload_capa = DEV_TX_OFFLOAD_MULTI_SEGS; + } + + devinfo->max_mac_addrs = OTX_EP_MAX_MAC_ADDRS; + + devinfo->rx_desc_lim = otx_ep_rx_desc_lim; + devinfo->tx_desc_lim = otx_ep_tx_desc_lim; + + return 0; +} + static int otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) { @@ -62,6 +110,37 @@ otx_epdev_init(struct otx_ep_device *otx_epvf) return -ENOMEM; } +static int +otx_ep_dev_configure(struct rte_eth_dev *eth_dev) +{ + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); + struct rte_eth_dev_data *data = eth_dev->data; + struct rte_eth_conf *conf = &data->dev_conf; + struct rte_eth_rxmode *rxmode = &conf->rxmode; + struct rte_eth_txmode *txmode = &conf->txmode; + uint32_t ethdev_queues; + + ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf); + if (eth_dev->data->nb_rx_queues > ethdev_queues || + eth_dev->data->nb_tx_queues > ethdev_queues) { + otx_ep_err("invalid num queues\n"); + return -ENOMEM; + } + otx_ep_info("OTX_EP Device is configured with num_txq %d num_rxq %d\n", + eth_dev->data->nb_rx_queues, eth_dev->data->nb_tx_queues); + + otx_epvf->port_configured = 1; + otx_epvf->rx_offloads = rxmode->offloads; + otx_epvf->tx_offloads = txmode->offloads; + + return 0; +} + +/* Define our ethernet definitions */ +static const struct eth_dev_ops otx_ep_eth_dev_ops = { + .dev_configure = otx_ep_dev_configure, + .dev_infos_get = otx_ep_dev_info_get, +}; static int otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev) @@ -105,6 +184,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) } otx_epvf->eth_dev = eth_dev; otx_epvf->port_id = eth_dev->data->port_id; + eth_dev->dev_ops = &otx_ep_eth_dev_ops; eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0); if (eth_dev->data->mac_addrs == NULL) { otx_ep_err("MAC addresses memory allocation failed\n"); diff --git a/drivers/net/octeontx_ep/otx_ep_rxtx.h b/drivers/net/octeontx_ep/otx_ep_rxtx.h new file mode 100644 index 0000000000..819204a763 --- /dev/null +++ b/drivers/net/octeontx_ep/otx_ep_rxtx.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _OTX_EP_RXTX_H_ +#define _OTX_EP_RXTX_H_ + +#define OTX_EP_RXD_ALIGN 1 +#define OTX_EP_TXD_ALIGN 1 +#endif