From patchwork Thu Dec 31 07:22:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pradeep Nalla X-Patchwork-Id: 85914 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F2B8DA0A00; Thu, 31 Dec 2020 08:23:06 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D2094140CED; Thu, 31 Dec 2020 08:23:00 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 20691140CD3 for ; Thu, 31 Dec 2020 08:22:57 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0BV7G5RA022206; Wed, 30 Dec 2020 23:22:57 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=nofnG0OOIliSpStsmPmwA8tROxQJYR0rEjBxOAqxtSQ=; b=CFGXeZc+CGMP98+kxnENG1zt298GmNcxYg/nbImFZAnGKmuHBgtIxLOfZqTCaXwiUAh+ wUFa5B5xbq9bwF6QzAv0mmku5JnssDWgFIo88S0Xx0JEgvBbPs2MxbjH5DynNXZJwu2u 5u4ex5nJkOTo9FT/mwELGSsObku18/RqvOegCmT4jR/v+WdwIjZwLwJJGkUSQ0yV0CxC jApSDjww2SBTjULyzVVk7NXNpo/q+z7Z6KRl4pRFtFB/AbqKQ/8DWPzinBAlhFL2409o Xma3NHVkt1Sewt6JZNdDHyyjG+ujyog8iLTuoJkUZP7f9452sPAG13yYAnYJ725DamL4 og== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 35rqgehx54-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 30 Dec 2020 23:22:57 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Dec 2020 23:22:55 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Dec 2020 23:22:55 -0800 Received: from localhost.localdomain (unknown [10.111.145.157]) by maili.marvell.com (Postfix) with ESMTP id 7B4723F703F; Wed, 30 Dec 2020 23:22:55 -0800 (PST) From: "Nalla, Pradeep" To: "Nalla, Pradeep" , Radha Mohan Chintakuntla , Veerasenareddy Burru , "Anatoly Burakov" CC: , , Date: Thu, 31 Dec 2020 07:22:35 +0000 Message-ID: <20201231072247.5719-4-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201231072247.5719-1-pnalla@marvell.com> References: <20201231072247.5719-1-pnalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-31_02:2020-12-30, 2020-12-31 signatures=0 Subject: [dpdk-dev] [PATCH 03/15] net/octeontx_ep: add device init and uninit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "Nalla Pradeep" Add basic init and uninit function which includes initializing fields of ethdev private structure. Signed-off-by: Nalla Pradeep --- drivers/net/octeontx_ep/otx_ep_common.h | 22 ++++++ drivers/net/octeontx_ep/otx_ep_ethdev.c | 99 ++++++++++++++++++++++++- 2 files changed, 117 insertions(+), 4 deletions(-) diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h index 7a1484f1aa..fca0c79a43 100644 --- a/drivers/net/octeontx_ep/otx_ep_common.h +++ b/drivers/net/octeontx_ep/otx_ep_common.h @@ -4,11 +4,33 @@ #ifndef _OTX_EP_COMMON_H_ #define _OTX_EP_COMMON_H_ +#define otx_ep_printf(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, RTE_LOGTYPE_PMD, \ + fmt, ##args) + +#define otx_ep_info(fmt, args...) \ + otx_ep_printf(INFO, fmt, ##args) + +#define otx_ep_err(fmt, args...) \ + otx_ep_printf(ERR, fmt, ##args) + +#define otx_ep_dbg(fmt, args...) \ + otx_ep_printf(DEBUG, fmt, ##args) + /* OTX_EP EP VF device data structure */ struct otx_ep_device { /* PCI device pointer */ struct rte_pci_device *pdev; + uint16_t chip_id; + uint16_t vf_num; struct rte_eth_dev *eth_dev; + + int port_id; + + /* Memory mapped h/w address */ + uint8_t *hw_addr; + + int port_configured; }; #endif /* _OTX_EP_COMMON_H_ */ diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c index 960c4f321e..6012c3fe9d 100644 --- a/drivers/net/octeontx_ep/otx_ep_ethdev.c +++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c @@ -10,20 +10,111 @@ #include "otx_ep_common.h" #include "otx_ep_vf.h" +#define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private) +static int +otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) +{ + struct rte_pci_device *pdev = otx_epvf->pdev; + uint32_t dev_id = pdev->id.device_id; + int ret; + + switch (dev_id) { + case PCI_DEVID_OCTEONTX_EP_VF: + otx_epvf->chip_id = PCI_DEVID_OCTEONTX_EP_VF; + break; + case PCI_DEVID_OCTEONTX2_EP_NET_VF: + case PCI_DEVID_98XX_EP_NET_VF: + otx_epvf->chip_id = dev_id; + break; + default: + otx_ep_err("Unsupported device\n"); + ret = -EINVAL; + } + + if (!ret) + otx_ep_info("OTX_EP dev_id[%d]\n", dev_id); + + return ret; +} + +/* OTX_EP VF device initialization */ +static int +otx_epdev_init(struct otx_ep_device *otx_epvf) +{ + if (otx_ep_chip_specific_setup(otx_epvf)) { + otx_ep_err("Chip specific setup failed\n"); + goto setup_fail; + } + + return 0; + +setup_fail: + return -ENOMEM; +} + + static int otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev) { - RTE_SET_USED(eth_dev); + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + otx_epvf->port_configured = 0; - return -ENODEV; + if (eth_dev->data->mac_addrs != NULL) + rte_free(eth_dev->data->mac_addrs); + + return 0; } + + static int otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) { - RTE_SET_USED(eth_dev); + struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); + int vf_id; + unsigned char vf_mac_addr[RTE_ETHER_ADDR_LEN]; + + /* Single process support */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rte_eth_copy_pci_info(eth_dev, pdev); + + if (pdev->mem_resource[0].addr) { + otx_ep_info("OTX_EP_EP BAR0 is mapped:\n"); + } else { + otx_ep_err("OTX_EP_EP: Failed to map device BARs\n"); + otx_ep_err("BAR0 %p\n BAR2 %p", + pdev->mem_resource[0].addr, + pdev->mem_resource[2].addr); + return -ENODEV; + } + otx_epvf->eth_dev = eth_dev; + otx_epvf->port_id = eth_dev->data->port_id; + eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0); + if (eth_dev->data->mac_addrs == NULL) { + otx_ep_err("MAC addresses memory allocation failed\n"); + return -ENOMEM; + } + rte_eth_random_addr(vf_mac_addr); + memcpy(eth_dev->data->mac_addrs, vf_mac_addr, RTE_ETHER_ADDR_LEN); + otx_epvf->hw_addr = pdev->mem_resource[0].addr; + otx_epvf->pdev = pdev; + + /* Discover the VF number being probed */ + vf_id = ((pdev->addr.devid & 0x1F) << 3) | + (pdev->addr.function & 0x7); + + vf_id -= 1; + otx_epvf->vf_num = vf_id; + otx_epdev_init(otx_epvf); + otx_epvf->port_configured = 0; - return -ENODEV; + return 0; } static int