From patchwork Sun Dec 20 05:24:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 85514 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C2E3A052A; Sun, 20 Dec 2020 06:25:54 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3B9D6CBAB; Sun, 20 Dec 2020 06:24:47 +0100 (CET) Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) by dpdk.org (Postfix) with ESMTP id 2AA95CB79 for ; Sun, 20 Dec 2020 06:24:42 +0100 (CET) Received: by mail-pg1-f179.google.com with SMTP id n10so4279556pgl.10 for ; Sat, 19 Dec 2020 21:24:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0maMfO4D/YWy1In3qE1QEmdvygAB0mx5Z081HoTJe18=; b=rV6usz/258H6A9u1XA3TUIpzM1amqo1FldO7eB0b+megJqZoqAalzs/ETKQFGmUK3X aGMWro/mEtHRcgzPxBcbgUIizpErCw+1tlYlOSAmNnRmLKDVfAeHb8wBDzlGm2TDAbk9 vy7UmsD4ilF0tOJPxR2MypNGBLbhPEMHzL25Yk/lEeZKULqWDcwDkThAa6fgtfsP9Tra 8nRZaUM/D4homLMArtbI6KxFbjpZGlZsGqXbX1yQkq+vZELhRwfLEz+BvMF7wHmRtc4P COEGpuJuJXqpmo/rxz0qbRqFKMNBpvoRfCJyrdI7FFoEablfwKxCZM5ezjs5CeAVLnu7 RTzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0maMfO4D/YWy1In3qE1QEmdvygAB0mx5Z081HoTJe18=; b=dbNe/JE3rDBqf70s9fSZSatzaVbo1sBcfF4m0zmgRznsgD5eTaoANypm1SoTiCHw9s P0wDvknbsZ8pCwnWWcfE7cr3sZuU68KzEXRbmK5naJ44agVHV23+/zgb0K/zRUX16AH6 mTEjON1qW9o4iQkiXiT4LUmDISTlLvmPIbi1A/kfxtwmnskeejf9/huIrfBG0fELSUf+ ddIiItDFggRM6uIABlNwcD7xRFYtF1srF0Az/deWF+ny8kvqvc1b/gr9HS5j5ZoLzvi4 QFL71haErPRh1cIGmUe4b+EABXcgiKNcjfsXpvwudbQwZJy3ySncfLDRlSI14ukaGvn8 z3SA== X-Gm-Message-State: AOAM530aAy8yeMxHEpHrMSLOHHV7GGdmX2iLy4JQzVjw2Uw2IOnYZFrF IV5xtXr1zZ4hxjLmgJvGCKISj8mVeI0msg== X-Google-Smtp-Source: ABdhPJzRO9dvONblHvSxaV9NYim3yKGAsqYUFguExv+6+exByN+lN55G2VNEII0SCCyLkC9iLvZI4g== X-Received: by 2002:a62:e818:0:b029:19e:31e6:e639 with SMTP id c24-20020a62e8180000b029019e31e6e639mr10295210pfi.81.1608441880113; Sat, 19 Dec 2020 21:24:40 -0800 (PST) Received: from localhost.localdomain ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id b11sm12936544pfr.38.2020.12.19.21.24.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 19 Dec 2020 21:24:39 -0800 (PST) From: Ajit Khaparde X-Google-Original-From: Ajit Khaparde To: dev@dpdk.org Cc: Kalesh AP Date: Sat, 19 Dec 2020 21:24:28 -0800 Message-Id: <20201220052430.99990-5-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20201220052430.99990-1-ajit.khaparde@broadcom.com> References: <20201220052430.99990-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 4/6] net/bnxt: add LRO support for SR2 chip X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP Add the new chip specific TPA v2 logic to bnxt_tpa_start() to fully support TPA on the new chip. Signed-off-by: Kalesh AP Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt_rxr.c | 72 +++++++++++++++++++++++++++++++------ drivers/net/bnxt/bnxt_rxr.h | 12 ++++++- 2 files changed, 72 insertions(+), 12 deletions(-) diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c index 288b403bf..96e995029 100644 --- a/drivers/net/bnxt/bnxt_rxr.c +++ b/drivers/net/bnxt/bnxt_rxr.c @@ -134,6 +134,53 @@ struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr, return mbuf; } +static void bnxt_tpa_get_metadata(struct bnxt *bp, + struct bnxt_tpa_info *tpa_info, + struct rx_tpa_start_cmpl *tpa_start, + struct rx_tpa_start_cmpl_hi *tpa_start1) +{ + tpa_info->cfa_code_valid = 0; + tpa_info->vlan_valid = 0; + tpa_info->hash_valid = 0; + tpa_info->l4_csum_valid = 0; + + if (likely(tpa_start->flags_type & + rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) { + tpa_info->hash_valid = 1; + tpa_info->rss_hash = rte_le_to_cpu_32(tpa_start->rss_hash); + } + + if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) { + struct rx_tpa_start_v2_cmpl *v2_tpa_start = (void *)tpa_start; + struct rx_tpa_start_v2_cmpl_hi *v2_tpa_start1 = + (void *)tpa_start1; + + if (v2_tpa_start->agg_id & + RX_TPA_START_V2_CMPL_METADATA1_VALID) { + tpa_info->vlan_valid = 1; + tpa_info->vlan = + rte_le_to_cpu_16(v2_tpa_start1->metadata0); + } + + if (v2_tpa_start1->flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK) + tpa_info->l4_csum_valid = 1; + + return; + } + + tpa_info->cfa_code_valid = 1; + tpa_info->cfa_code = rte_le_to_cpu_16(tpa_start1->cfa_code); + if (tpa_start1->flags2 & + rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) { + tpa_info->vlan_valid = 1; + tpa_info->vlan = rte_le_to_cpu_32(tpa_start1->metadata); + } + + if (likely(tpa_start1->flags2 & + rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC))) + tpa_info->l4_csum_valid = 1; +} + static void bnxt_tpa_start(struct bnxt_rx_queue *rxq, struct rx_tpa_start_cmpl *tpa_start, struct rx_tpa_start_cmpl_hi *tpa_start1) @@ -164,21 +211,23 @@ static void bnxt_tpa_start(struct bnxt_rx_queue *rxq, mbuf->data_len = mbuf->pkt_len; mbuf->port = rxq->port_id; mbuf->ol_flags = PKT_RX_LRO; - if (likely(tpa_start->flags_type & - rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) { - mbuf->hash.rss = rte_le_to_cpu_32(tpa_start->rss_hash); + + bnxt_tpa_get_metadata(rxq->bp, tpa_info, tpa_start, tpa_start1); + + if (likely(tpa_info->hash_valid)) { + mbuf->hash.rss = tpa_info->rss_hash; mbuf->ol_flags |= PKT_RX_RSS_HASH; - } else { - mbuf->hash.fdir.id = rte_le_to_cpu_16(tpa_start1->cfa_code); + } else if (tpa_info->cfa_code_valid) { + mbuf->hash.fdir.id = tpa_info->cfa_code; mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID; } - if (tpa_start1->flags2 & - rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) { - mbuf->vlan_tci = rte_le_to_cpu_32(tpa_start1->metadata); + + if (tpa_info->vlan_valid) { + mbuf->vlan_tci = tpa_info->vlan; mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; } - if (likely(tpa_start1->flags2 & - rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC))) + + if (likely(tpa_info->l4_csum_valid)) mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD; /* recycle next mbuf */ @@ -712,7 +761,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt, cpr->cp_ring_struct->ring_mask, cpr->valid); - if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START) { + if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START || + cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2) { bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp, (struct rx_tpa_start_cmpl_hi *)rxcmp1); rc = -EINVAL; /* Continue w/o new mbuf */ diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h index af6ff0972..7ca7e39e5 100644 --- a/drivers/net/bnxt/bnxt_rxr.h +++ b/drivers/net/bnxt/bnxt_rxr.h @@ -47,6 +47,14 @@ struct bnxt_tpa_info { uint16_t len; uint32_t agg_count; struct rx_tpa_v2_abuf_cmpl agg_arr[TPA_MAX_NUM_SEGS]; + + uint32_t rss_hash; + uint32_t vlan; + uint16_t cfa_code; + uint8_t hash_valid:1; + uint8_t vlan_valid:1; + uint8_t cfa_code_valid:1; + uint8_t l4_csum_valid:1; }; struct bnxt_rx_ring_info { @@ -122,4 +130,6 @@ extern uint32_t bnxt_ol_flags_table[BNXT_OL_FLAGS_TBL_DIM]; #define BNXT_OL_FLAGS_ERR_TBL_DIM 16 extern uint32_t bnxt_ol_flags_err_table[BNXT_OL_FLAGS_ERR_TBL_DIM]; -#endif + +#define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK (0x1 << 14) +#endif /* _BNXT_RXR_H_ */