From patchwork Sun Dec 20 05:24:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 85513 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D1823A052A; Sun, 20 Dec 2020 06:25:36 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8C95FCB89; Sun, 20 Dec 2020 06:24:45 +0100 (CET) Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) by dpdk.org (Postfix) with ESMTP id DC025CB2F for ; Sun, 20 Dec 2020 06:24:40 +0100 (CET) Received: by mail-pg1-f170.google.com with SMTP id n7so4303618pgg.2 for ; Sat, 19 Dec 2020 21:24:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7CF7wjFeCjl7zOahbAJm+gVEu5lGZ3LdjcDXoVa4RKk=; b=juAS05xvovzjq5UkMfUaEwci4eGJ5Y4BRmB76O/TccLuZ6E8a1nCZYoqMEriaxpWae gcPDhNB/ORq6xwIuO9PFclmosDIln7DM6igwkEUJx6kSymdi+iv2qbkzrozF2Vt8IDvy Q5gMn0yk2vxSdG02BNyLOs3apYKql8z6ReAga3M0lFrqyoICEbJ3PNfnWJo8zB/qqs94 03ypAEBc1BD+xKNoA3NjB17WAMI5DyCGtsCtaujnMKhE51O9qTTg8b15FIhjruMmj1os LjGVrkazTsf4q3h6ovvx8+Wv7QsYku4XzSW24RRsKswXWjQNyyJllOqDwk6e4tsN2wdh nOaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7CF7wjFeCjl7zOahbAJm+gVEu5lGZ3LdjcDXoVa4RKk=; b=SVuWdiM+jRLAX1ScUHmF2h0cqJHpxqsdnL/ZlAQCbZNt73+mDlJX9nK8XnFeztvoeS 8NNnIrpmLR7cMBHQSLAXNxb1Lrrn2qY1i7YPDrJWnfLUGznwOETdAtWyHHfMlj0ZrZ5E dZe/BgOwPV1m7QyUX05xzoA8PWd8YQDeDCcolcz0DNg3KlpUXC/y5soWW+x8bW8658ms 2zYxHBXhMlQIoqguP+jL/BxSR0GZOHFZORjwyQ7cw+Wo43P5VXnSvkFqSCRj+E5X4A2n 0wAGkhJly78aFS5LMHbzzIyjnLjYECPUeQZJIwccMzyZF2HkvStnCoSZ6+KJSk4r0DVb 38VA== X-Gm-Message-State: AOAM533kspIk3/NHc/U0Y7vSuv1QWqGjnZ1jkdarmoGoS+vGuvErT3aF i8AT63wyLeozbanyt5IS/RJDKC7+67vrJQ== X-Google-Smtp-Source: ABdhPJzYC6J/CMedx+hqDzQF6YpyOUEaR0VFbIcGTRgc6NR8uinEeWL5FopMEBC3NjzoYt5AbIJP9Q== X-Received: by 2002:aa7:959a:0:b029:1a1:ffc5:531d with SMTP id z26-20020aa7959a0000b02901a1ffc5531dmr10437555pfj.27.1608441878735; Sat, 19 Dec 2020 21:24:38 -0800 (PST) Received: from localhost.localdomain ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id b11sm12936544pfr.38.2020.12.19.21.24.37 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 19 Dec 2020 21:24:38 -0800 (PST) From: Ajit Khaparde X-Google-Original-From: Ajit Khaparde To: dev@dpdk.org Cc: Kalesh AP Date: Sat, 19 Dec 2020 21:24:27 -0800 Message-Id: <20201220052430.99990-4-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20201220052430.99990-1-ajit.khaparde@broadcom.com> References: <20201220052430.99990-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 3/6] net/bnxt: modify VNIC accounting X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP Modify VNIC accounting when enabling RFS on newer chips. Unlike legacy chips, newer chips don't need additional VNIC resources for ntuple filter. Fix the code accordingly so that we don't reserve and allocate additional VNICs on newer chips. Signed-off-by: Kalesh AP Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt.h | 3 +++ drivers/net/bnxt/bnxt_ethdev.c | 18 ++++++++++++++---- drivers/net/bnxt/bnxt_flow.c | 14 ++++++++++++-- drivers/net/bnxt/bnxt_hwrm.c | 32 ++++++++++++++++++++++++++++++++ drivers/net/bnxt/bnxt_hwrm.h | 5 +++-- 5 files changed, 64 insertions(+), 8 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 14f52b2c4..276d807c7 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -643,6 +643,9 @@ struct bnxt { #define BNXT_FLAG_DFLT_MAC_SET BIT(26) #define BNXT_FLAG_TRUFLOW_EN BIT(27) #define BNXT_FLAG_GFID_ENABLE BIT(28) +#define BNXT_FLAG_RFS_NEEDS_VNIC BIT(29) +#define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(30) +#define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC) #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 02ab87bba..8ca4fb151 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -748,11 +748,17 @@ static int bnxt_init_chip(struct bnxt *bp) goto err_out; } + /* default vnic 0 */ + rc = bnxt_setup_one_vnic(bp, 0); + if (rc) + goto err_out; /* VNIC configuration */ - for (i = 0; i < bp->nr_vnics; i++) { - rc = bnxt_setup_one_vnic(bp, i); - if (rc) - goto err_out; + if (BNXT_RFS_NEEDS_VNIC(bp)) { + for (i = 1; i < bp->nr_vnics; i++) { + rc = bnxt_setup_one_vnic(bp, i); + if (rc) + goto err_out; + } } rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); @@ -4698,6 +4704,10 @@ static int bnxt_init_fw(struct bnxt *bp) if (rc) return rc; + rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); + if (rc) + return rc; + bnxt_hwrm_port_mac_qcfg(bp); bnxt_hwrm_parent_pf_qcfg(bp); diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c index 127d51c45..07d359edf 100644 --- a/drivers/net/bnxt/bnxt_flow.c +++ b/drivers/net/bnxt/bnxt_flow.c @@ -1056,6 +1056,13 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev, } PMD_DRV_LOG(DEBUG, "Queue index %d\n", act_q->index); + if (use_ntuple && !BNXT_RFS_NEEDS_VNIC(bp)) { + filter->flags = + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX; + filter->dst_id = act_q->index; + goto skip_vnic_alloc; + } + vnic_id = attr->group; if (!vnic_id) { PMD_DRV_LOG(DEBUG, "Group id is 0\n"); @@ -1127,7 +1134,7 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev, PMD_DRV_LOG(DEBUG, "Setting vnic ff_idx %d\n", vnic->ff_pool_idx); filter->dst_id = vnic->fw_vnic_id; - +skip_vnic_alloc: /* For ntuple filter, create the L2 filter with default VNIC. * The user specified redirect queue will be set while creating * the ntuple filter in hardware. @@ -1808,7 +1815,10 @@ bnxt_flow_create(struct rte_eth_dev *dev, } } - vnic = find_matching_vnic(bp, filter); + if (BNXT_RFS_NEEDS_VNIC(bp)) + vnic = find_matching_vnic(bp, filter); + else + vnic = BNXT_GET_DEFAULT_VNIC(bp); done: if (!ret || update_flow) { flow->filter = filter; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 350fe2f97..56e2e33a9 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -5834,3 +5834,35 @@ int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp) rep_bp->vf_id); return rc; } + +int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp) +{ + struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp = + bp->hwrm_cmd_resp_addr; + struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; + uint32_t flags = 0; + int rc = 0; + + if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT)) + return 0; + + if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) { + PMD_DRV_LOG(DEBUG, + "Not a PF or trusted VF. Command not supported\n"); + return 0; + } + + HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + + HWRM_CHECK_RESULT(); + flags = rte_le_to_cpu_32(resp->flags); + HWRM_UNLOCK(); + + if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED) + bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2; + else + bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC; + + return rc; +} diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 4b3290773..7deea29ca 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -55,8 +55,8 @@ struct hwrm_func_qstats_output; #define HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK \ HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK -#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN \ -HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED +#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED \ + HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED #define HWRM_SPEC_CODE_1_8_4 0x10804 #define HWRM_SPEC_CODE_1_9_0 0x10900 @@ -300,4 +300,5 @@ int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid, uint16_t *first_vf_id); int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep); int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep); +int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp); #endif