diff mbox series

[2/6] net/bnxt: add new RX checksum mode

Message ID 20201220052430.99990-3-ajit.khaparde@broadcom.com (mailing list archive)
State Superseded, archived
Delegated to: Ajit Khaparde
Headers show
Series net/bnxt: add support for Stingray2 | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Ajit Khaparde Dec. 20, 2020, 5:24 a.m. UTC
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>

The 58818 chips support two different checksum modes.
Host driver has to register with FW which checksum mode it
prefers to use. DPDK driver want to use "cs_all_ok_mode=1".
FW advertises the support of the different checksum modes
on per VNIC basis in the HWRM_VNIC_QCAPS response.
Driver should use HWRM_VNIC_CFG to configure the needed
checksum mode.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/bnxt.h      | 1 +
 drivers/net/bnxt/bnxt_hwrm.c | 8 ++++++++
 2 files changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 0d3998f20..14f52b2c4 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -679,6 +679,7 @@  struct bnxt {
 	uint32_t		vnic_cap_flags;
 #define BNXT_VNIC_CAP_COS_CLASSIFY	BIT(0)
 #define BNXT_VNIC_CAP_OUTER_RSS		BIT(1)
+#define BNXT_VNIC_CAP_RX_CMPL_V2	BIT(2)
 	unsigned int		rx_nr_rings;
 	unsigned int		rx_cp_nr_rings;
 	unsigned int		rx_num_qs_per_vnic;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 36c229de1..350fe2f97 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -860,6 +860,9 @@  int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 	if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 		bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
 
+	if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
+		bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
+
 	bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 
 	HWRM_UNLOCK();
@@ -1961,6 +1964,11 @@  int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 			rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
 		enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
 			  HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
+		if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
+			enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
+			req.rx_csum_v2_mode =
+				HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
+		}
 		goto config_mru;
 	}