diff mbox series

[27/35] net/mlx5/windows: create flow rule

Message ID 20201217173037.11396-28-talshn@nvidia.com (mailing list archive)
State Superseded, archived
Delegated to: Raslan Darawsheh
Headers show
Series mlx5 Windows support - part #6 | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Tal Shnaiderman Dec. 17, 2020, 5:30 p.m. UTC
From: Ophir Munk <ophirmu@nvidia.com>

This commit implements mlx5_flow_os_create_flow() API. It is equivalent
to Linux rdma-core implementation. The API receives the matcher mask,
matcher value and an array of actions. They are copied into a PRM-like
struct devx_fs_rule_add_in. Then glue API devx_fs_rule_add() is called.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/common/mlx5/mlx5_prm.h          |  6 +++++
 drivers/net/mlx5/windows/mlx5_flow_os.c | 46 ++++++++++++++++++++++++++-------
 2 files changed, 42 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index ac42238d30..8c9b53ce10 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -825,6 +825,12 @@  struct mlx5_ifc_fte_match_param_bits {
 #endif
 };
 
+struct mlx5_ifc_dest_format_struct_bits {
+	u8 destination_type[0x8];
+	u8 destination_id[0x18];
+	u8 reserved_0[0x20];
+};
+
 enum {
 	MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
 	MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.c b/drivers/net/mlx5/windows/mlx5_flow_os.c
index 0c0fba3720..daf4e15ddb 100644
--- a/drivers/net/mlx5/windows/mlx5_flow_os.c
+++ b/drivers/net/mlx5/windows/mlx5_flow_os.c
@@ -187,13 +187,41 @@  mlx5_flow_os_create_flow(void *matcher, void *match_value,
 			 size_t num_actions,
 			 void *actions[], void **flow)
 {
-	RTE_SET_USED(matcher);
-	RTE_SET_USED(match_value);
-	RTE_SET_USED(num_actions);
-	RTE_SET_USED(actions);
-	*flow = NULL;
-	rte_errno = ENOTSUP;
-	return -rte_errno;
+	struct mlx5_action *action;
+	int i;
+	struct mlx5_matcher *mlx5_matcher = matcher;
+	struct mlx5_flow_dv_match_params *mlx5_match_value = match_value;
+	uint32_t in[MLX5_ST_SZ_DW(devx_fs_rule_add_in)] = {0};
+	void *matcher_c = MLX5_ADDR_OF(devx_fs_rule_add_in, in,
+				       match_criteria);
+	void *matcher_v = MLX5_ADDR_OF(devx_fs_rule_add_in, in,
+				       match_value);
+
+	MLX5_ASSERT(mlx5_matcher->ctx);
+	memcpy(matcher_c, mlx5_matcher->match_buf,
+	       mlx5_match_value->size);
+	/* Use mlx5_match_value->size for match criteria */
+	memcpy(matcher_v, mlx5_match_value->buf,
+	       mlx5_match_value->size);
+	for (i = 0; i < num_actions; i++) {
+		action = actions[i];
+		switch (action->type) {
+		case MLX5_FLOW_CONTEXT_DEST_TYPE_TIR:
+			MLX5_SET(devx_fs_rule_add_in, in,
+				 dest.destination_type,
+				 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR);
+			MLX5_SET(devx_fs_rule_add_in, in,
+				 dest.destination_id,
+				 action->dest_tir.id);
+			break;
+		default:
+			break;
+		}
+		MLX5_SET(devx_fs_rule_add_in, in, match_criteria_enable,
+			 MLX5_MATCH_OUTER_HEADERS);
+	}
+	*flow = mlx5_glue->devx_fs_rule_add(mlx5_matcher->ctx, in, sizeof(in));
+	return (*flow) ? 0 : -1;
 }
 
 /**
@@ -208,7 +236,5 @@  mlx5_flow_os_create_flow(void *matcher, void *match_value,
 int
 mlx5_flow_os_destroy_flow(void *drv_flow_ptr)
 {
-	RTE_SET_USED(dev_flow_ptr);
-	rte_errno = ENOTSUP;
-	return -rte_errno;
+	return mlx5_glue->devx_fs_rule_del(drv_flow_ptr);
 }