diff mbox series

[02/27] net/ice/base: increased control queue timeout

Message ID	20201215060519.302145-3-qi.z.zhang@intel.com (mailing list archive)
State	Accepted, archived
Delegated to:	Qi Zhang
Headers	IronPort-SDR: SKCogV7bS4QexsEaGw8lxhzo+BANrb8CqNW2YTNxGEQoR0ls0NNwnlGmtxYaLYatiWOPJ6WCWM lirQOHFJh6Kw== IronPort-SDR: Ebiw0sBLnL6ekYtAytm0y/iEvfCv5F2GzY9yc72iNLQaVubHUbFE68xc9speRnuzJidb0kJF1s +F8hViLwxsSw== From: Qi Zhang <qi.z.zhang@intel.com> To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>, Fabio Pricoco <fabio.pricoco@intel.com> Date: Tue, 15 Dec 2020 14:04:54 +0800 Message-Id: <20201215060519.302145-3-qi.z.zhang@intel.com> In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 02/27] net/ice/base: increased control queue timeout Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	ice base code update \| [00/27] ice base code update [01/27] net/ice/base: modify ptype map for UDP [02/27] net/ice/base: increased control queue timeout [03/27] net/ice/base: read more security revision options [04/27] net/ice/base: refactor interface for flash read [05/27] net/ice/base: allow reading inactive flash security revision [06/27] net/ice/base: allow reading arbitrary size data with flash read [07/27] net/ice/base: read Option ROM combo version from CIVD section [08/27] net/ice/base: implement inactive NVM version get [09/27] net/ice/base: support GTP filtering via advanced switch filter [10/27] net/ice/base: cleanup some macros [11/27] net/ice/base: add definitions for FW health status codes [12/27] net/ice/base: add function for NVM checksum verification [13/27] net/ice/base: add condition to copy module info into memory [14/27] net/ice/base: add interface to support configuring VLAN mode [15/27] net/ice/base: support VXLAN VNI field in FDIR [16/27] net/ice/base: fix incorrect tunnel destroy [17/27] net/ice/base: add functionality to check if DVM is supported [18/27] net/ice/base: resend some AQ commands when EBUSY [19/27] net/ice/base: change get PHY capability error level [20/27] net/ice/base: modify recursive way of adding nodes [21/27] net/ice/base: fix for dereference of null pointer [22/27] net/ice/base: use Mode 4 to get PHY Abilites [23/27] net/ice/base: align macro names to the specification [24/27] net/ice/base: add eCPRI over MAC type 0 flow support [25/27] net/ice/base: add eCPRI over UDP type 0 flow support [26/27] net/ice/base: remove unused struct member [27/27] net/ice/base: change a structure

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Qi Zhang Dec. 15, 2020, 6:04 a.m. UTC

  250 msec timeout is insufficient for some AQ commands. Advice from FW
team was to increase the timeout. Increased to 1 second.

Signed-off-by: Fabio Pricoco <fabio.pricoco@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_controlq.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h
index e5e0001788..84c114f7a4 100644
--- a/drivers/net/ice/base/ice_controlq.h
+++ b/drivers/net/ice/base/ice_controlq.h
@@ -32,8 +32,8 @@  enum ice_ctl_q {
 	ICE_CTL_Q_MAILBOX,
 };
 
-/* Control Queue timeout settings - max delay 250ms */
-#define ICE_CTL_Q_SQ_CMD_TIMEOUT	2500  /* Count 2500 times */
+/* Control Queue timeout settings - max delay 1s */
+#define ICE_CTL_Q_SQ_CMD_TIMEOUT	10000 /* Count 10000 times */
 #define ICE_CTL_Q_SQ_CMD_USEC		100   /* Check every 100usec */
 #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT	10    /* Count 10 times */
 #define ICE_CTL_Q_ADMIN_INIT_MSEC	100   /* Check every 100msec */