From patchwork Tue Nov 3 08:28:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Yang X-Patchwork-Id: 83499 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B5C57A0521; Tue, 3 Nov 2020 09:30:42 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0C007C7FC; Tue, 3 Nov 2020 09:29:50 +0100 (CET) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id EA845C828 for ; Tue, 3 Nov 2020 09:29:47 +0100 (CET) IronPort-SDR: +/yTC7VTMwQVZtuhE9R4kCm80HVSaNnMgi3L7cTCUIKe+vlhOP1iyb8E6RGyp2sgI5XB++geub LOB3sXoTaglg== X-IronPort-AV: E=McAfee;i="6000,8403,9793"; a="169122346" X-IronPort-AV: E=Sophos;i="5.77,447,1596524400"; d="scan'208";a="169122346" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2020 00:29:47 -0800 IronPort-SDR: Bv1t5/J0GTjGLfO2Zq466EaeeP+DeDmWuh6lwdNbed2gdMOUJPf/6R3gA6io36VZh1tb85RBtB vDJqaVEqa35A== X-IronPort-AV: E=Sophos;i="5.77,447,1596524400"; d="scan'208";a="470711464" Received: from intel-npg-odc-srv01.cd.intel.com ([10.240.178.136]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2020 00:29:45 -0800 From: Steve Yang To: dev@dpdk.org Cc: jia.guo@intel.com, haiyue.wang@intel.com, qiming.yang@intel.com, beilei.xing@intel.com, orika@nvidia.com, murphyx.yang@intel.com, Steve Yang Date: Tue, 3 Nov 2020 08:28:07 +0000 Message-Id: <20201103082809.41149-5-stevex.yang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201103082809.41149-1-stevex.yang@intel.com> References: <20201014084131.72035-1-simonx.lu@intel.com> <20201103082809.41149-1-stevex.yang@intel.com> Subject: [dpdk-dev] [RFC v2 4/6] net/ixgbe: add mirror rule config and add/del rule APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Define ixgbe_flow_mirror_conf structure that is used for set mirror flow rule to ixgbe register, and relocate the mirror related MACORs to header file. Signed-off-by: Steve Yang --- drivers/net/ixgbe/ixgbe_ethdev.c | 8 ----- drivers/net/ixgbe/ixgbe_ethdev.h | 54 ++++++++++++++++++++++++++++++-- 2 files changed, 52 insertions(+), 10 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 9a47a8b26..cc07b0e31 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -5724,14 +5724,6 @@ ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) return new_val; } -#define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ -#define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ -#define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ -#define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ -#define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ - ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ - ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) - static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, struct rte_eth_mirror_conf *mirror_conf, diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h index 3d35ea791..db95a53f1 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.h +++ b/drivers/net/ixgbe/ixgbe_ethdev.h @@ -216,6 +216,27 @@ struct ixgbe_rte_flow_rss_conf { uint16_t queue[IXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */ }; +#define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */ +#define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ +#define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ +#define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ +#define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ +#define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ + ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP |\ + ETH_MIRROR_UPLINK_PORT | \ + ETH_MIRROR_DOWNLINK_PORT | \ + ETH_MIRROR_VLAN)) + +struct ixgbe_flow_mirror_conf { + uint8_t rule_type; + uint16_t rule_id; + uint8_t dst_pool; /* Destination pool for this mirror rule. */ + uint64_t pool_mask; /* Bitmap of pool for virtual pool mirroring */ + uint64_t vlan_mask; /* mask for valid VLAN ID. */ + /* VLAN ID list for vlan mirroring. */ + uint16_t vlan_id[ETH_MIRROR_MAX_VLANS]; +}; + /* structure for interrupt relative data */ struct ixgbe_interrupt { uint32_t flags; @@ -250,8 +271,6 @@ struct ixgbe_uta_info { uint32_t uta_shadow[IXGBE_MAX_UTA]; }; -#define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */ - struct ixgbe_mirror_info { struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES]; /**< store PF mirror rules configuration*/ @@ -337,6 +356,8 @@ struct ixgbe_filter_info { uint32_t syn_info; /* store the rss filter info */ struct ixgbe_rte_flow_rss_conf rss_info; + uint8_t mirror_mask; /* Bit mask for every used mirror filter */ + struct ixgbe_flow_mirror_conf mirror_filters[IXGBE_MAX_MIRROR_RULES]; }; struct ixgbe_l2_tn_key { @@ -830,4 +851,33 @@ ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info, return idx; } +static inline int8_t +ixgbe_mirror_filter_insert(struct ixgbe_filter_info *filter_info, + struct ixgbe_flow_mirror_conf *mirror_conf) +{ + int i; + + for (i = 0; i < IXGBE_MAX_MIRROR_RULES; i++) { + if (!(filter_info->mirror_mask & (1 << i))) { + filter_info->mirror_mask |= 1 << i; + mirror_conf->rule_id = i; + filter_info->mirror_filters[i] = *mirror_conf; + return i; + } + } + return -1; +} + +static inline int +ixgbe_mirror_filter_remove(struct ixgbe_filter_info *filter_info, + uint8_t idx) +{ + if (idx >= IXGBE_MAX_MIRROR_RULES) + return -1; + filter_info->mirror_mask &= ~(1 << idx); + memset(&filter_info->mirror_filters[idx], 0, + sizeof(filter_info->mirror_filters[0])); + return idx; +} + #endif /* _IXGBE_ETHDEV_H_ */