From patchwork Sun Oct 25 00:29:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 82083 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8E8A6A04B5; Sun, 25 Oct 2020 02:31:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F33173772; Sun, 25 Oct 2020 02:26:37 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id A6B2B2BA3 for ; Sun, 25 Oct 2020 02:26:21 +0200 (CEST) IronPort-SDR: T/Q/q/0S1tF1rcObnGiSxV1ZbeYFmAW5q4pxDItHFI4UGVeY/buJa/HegdRljDndy4tzSLWniA t7Fn5+OhkD0w== X-IronPort-AV: E=McAfee;i="6000,8403,9784"; a="167927045" X-IronPort-AV: E=Sophos;i="5.77,414,1596524400"; d="scan'208";a="167927045" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2020 17:26:20 -0700 IronPort-SDR: McJ+Ejpr3zsyyezYi+/KKKZ1S6etWTG6UGbHa9QXrLwsyYEbFgRONTGfk9UeYEWgNCevcgu/8L OhKpk3C0YxMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,414,1596524400"; d="scan'208";a="359984099" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by FMSMGA003.fm.intel.com with ESMTP; 24 Oct 2020 17:26:19 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Amir Shay Date: Sun, 25 Oct 2020 08:29:48 +0800 Message-Id: <20201025002953.1680999-17-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20201025002953.1680999-1-qi.z.zhang@intel.com> References: <20201025002953.1680999-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 16/21] net/ice/base: support extended GPIO access X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added two new admin commands called: SW Set GPIO and SW Get GPIO (0x6EF and 0x6F0 respectively) which extends GPIO handling capabilities by SW driver Signed-off-by: Amir Shay Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index c105a445ee..f715fb0910 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1635,6 +1635,22 @@ struct ice_aqc_sff_eeprom { __le32 addr_low; }; +/* SW Set GPIO command (indirect 0x6EF) + * SW Get GPIO command (indirect 0x6F0) + */ +struct ice_aqc_sw_gpio { + __le16 gpio_ctrl_handle; +#define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 +#define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) + u8 gpio_num; +#define ICE_AQC_SW_GPIO_NUMBER_S 0 +#define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) + u8 gpio_params; +#define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) +#define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) + u8 rsvd[12]; +}; + /* NVM Read command (indirect 0x0701) * NVM Erase commands (direct 0x0702) * NVM Write commands (indirect 0x0703) @@ -2925,6 +2941,8 @@ enum ice_adminq_opc { ice_aqc_opc_set_gpio = 0x06EC, ice_aqc_opc_get_gpio = 0x06ED, ice_aqc_opc_sff_eeprom = 0x06EE, + ice_aqc_opc_sw_set_gpio = 0x06EF, + ice_aqc_opc_sw_get_gpio = 0x06F0, /* NVM commands */ ice_aqc_opc_nvm_read = 0x0701,