From patchwork Tue Oct 20 22:48:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 81638 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DD332A04DD; Wed, 21 Oct 2020 00:47:11 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 23155ACCE; Wed, 21 Oct 2020 00:45:11 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 22881ACB0 for ; Wed, 21 Oct 2020 00:45:01 +0200 (CEST) IronPort-SDR: 8C2ruMUCM1ydtsTD2o0ZBCxXl89VTRMzJE3EU4LkxtNrUIX6CDDQRpo/aaqLD9HVtVZ86FjvbM i6VpGooD5U6w== X-IronPort-AV: E=McAfee;i="6000,8403,9780"; a="166510589" X-IronPort-AV: E=Sophos;i="5.77,399,1596524400"; d="scan'208";a="166510589" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2020 15:45:01 -0700 IronPort-SDR: SyL0WRrEYrH+cUF+7OUawgbkG+Nlsg3YM04anXVUzL73hpFtQokF0zDDzhyZGBlmIJdhTu3R7t kV2OzMGSR3Qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,399,1596524400"; d="scan'208";a="533254556" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga005.jf.intel.com with ESMTP; 20 Oct 2020 15:45:00 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Brett Creeley Date: Wed, 21 Oct 2020 06:48:32 +0800 Message-Id: <20201020224846.1592682-8-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20201020224846.1592682-1-qi.z.zhang@intel.com> References: <20201020224846.1592682-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 07/21] net/ice/base: add functions to allocate and free a RSS global LUT X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently there is no API to allocate and free a RSS global LUT. Incoming changes to support VFs having >16 queues will require using RSS global LUT resources. The functions included will allow a PF to configure a RSS global LUT for VFs that request >16 queues. Signed-off-by: Brett Creeley Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.c | 65 +++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_switch.h | 2 + 2 files changed, 67 insertions(+) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 01d59edf42..cd78685735 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -1848,6 +1848,71 @@ ice_aq_get_sw_cfg(struct ice_hw *hw, struct ice_aqc_get_sw_cfg_resp_elem *buf, return status; } +/** + * ice_alloc_rss_global_lut - allocate a RSS global LUT + * @hw: pointer to the HW struct + * @shared_res: true to allocate as a shared resource and false to allocate as a dedicated resource + * @global_lut_id: output parameter for the RSS global LUT's ID + */ +enum ice_status ice_alloc_rss_global_lut(struct ice_hw *hw, bool shared_res, u16 *global_lut_id) +{ + struct ice_aqc_alloc_free_res_elem *sw_buf; + enum ice_status status; + u16 buf_len; + + buf_len = ice_struct_size(sw_buf, elem, 1); + sw_buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); + if (!sw_buf) + return ICE_ERR_NO_MEMORY; + + sw_buf->num_elems = CPU_TO_LE16(1); + sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH | + (shared_res ? ICE_AQC_RES_TYPE_FLAG_SHARED : + ICE_AQC_RES_TYPE_FLAG_DEDICATED)); + + status = ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len, ice_aqc_opc_alloc_res, NULL); + if (status) { + ice_debug(hw, ICE_DBG_RES, "Failed to allocate %s RSS global LUT, status %d\n", + shared_res ? "shared" : "dedicated", status); + goto ice_alloc_global_lut_exit; + } + + *global_lut_id = LE16_TO_CPU(sw_buf->elem[0].e.sw_resp); + +ice_alloc_global_lut_exit: + ice_free(hw, sw_buf); + return status; +} + +/** + * ice_free_global_lut - free a RSS global LUT + * @hw: pointer to the HW struct + * @global_lut_id: ID of the RSS global LUT to free + */ +enum ice_status ice_free_rss_global_lut(struct ice_hw *hw, u16 global_lut_id) +{ + struct ice_aqc_alloc_free_res_elem *sw_buf; + u16 buf_len, num_elems = 1; + enum ice_status status; + + buf_len = ice_struct_size(sw_buf, elem, num_elems); + sw_buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); + if (!sw_buf) + return ICE_ERR_NO_MEMORY; + + sw_buf->num_elems = CPU_TO_LE16(num_elems); + sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH); + sw_buf->elem[0].e.sw_resp = CPU_TO_LE16(global_lut_id); + + status = ice_aq_alloc_free_res(hw, num_elems, sw_buf, buf_len, ice_aqc_opc_free_res, NULL); + if (status) + ice_debug(hw, ICE_DBG_RES, "Failed to free RSS global LUT %d, status %d\n", + global_lut_id, status); + + ice_free(hw, sw_buf); + return status; +} + /** * ice_alloc_sw - allocate resources specific to switch * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index a7e94344c1..be9b74fd4c 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -418,6 +418,8 @@ ice_free_res_cntr(struct ice_hw *hw, u8 type, u8 alloc_shared, u16 num_items, /* Switch/bridge related commands */ enum ice_status ice_update_sw_rule_bridge_mode(struct ice_hw *hw); +enum ice_status ice_alloc_rss_global_lut(struct ice_hw *hw, bool shared_res, u16 *global_lut_id); +enum ice_status ice_free_rss_global_lut(struct ice_hw *hw, u16 global_lut_id); enum ice_status ice_alloc_sw(struct ice_hw *hw, bool ena_stats, bool shared_res, u16 *sw_id, u16 *counter_id);