diff mbox series

[RFC,1/5] net/i40e: decouple dependency from superseded structures

Message ID 20200929074908.39915-1-chenxux.di@intel.com (mailing list archive)
State Superseded
Delegated to: Qi Zhang
Headers show
Series [RFC,1/5] net/i40e: decouple dependency from superseded structures | expand

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Chenxu Di Sept. 29, 2020, 7:49 a.m. UTC
From: Junyu Jiang <junyux.jiang@intel.com>

The legacy filter API will be removed, the associated rte_eth_ctrl.h
will also be removed. This patch replaces these superseded structures
by the PMD internal structures. The macros RTE_ETH_FILTER_GENERIC and
RTE_ETH_FILTER_GET are not replaced, they are needed to follow librte
to change.

Signed-off-by: Junyu Jiang <junyux.jiang@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c  | 312 ++++++++++++++--------------
 drivers/net/i40e/i40e_ethdev.h  | 357 +++++++++++++++++++++++++++++---
 drivers/net/i40e/i40e_fdir.c    |   8 +-
 drivers/net/i40e/i40e_flow.c    | 111 +++++-----
 drivers/net/i40e/i40e_pf.c      |   2 +-
 drivers/net/i40e/rte_pmd_i40e.c |  30 +--
 6 files changed, 559 insertions(+), 261 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 6439baf2f..8b95e70da 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -383,7 +383,7 @@  static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 
 static int i40e_ethertype_filter_convert(
-	const struct rte_eth_ethertype_filter *input,
+	const struct i40e_eth_ethertype_filter *input,
 	struct i40e_ethertype_filter *filter);
 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 				   struct i40e_ethertype_filter *filter);
@@ -2737,7 +2737,7 @@  i40e_dev_close(struct rte_eth_dev *dev)
 	while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
 		TAILQ_REMOVE(&pf->flow_list, p_flow, node);
 		/* Do not free FDIR flows since they are static allocated */
-		if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
+		if (p_flow->filter_type != I40E_ETH_FILTER_FDIR)
 			rte_free(p_flow);
 	}
 
@@ -4331,9 +4331,9 @@  i40e_macaddr_add(struct rte_eth_dev *dev,
 
 	rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 	if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
-		mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+		mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
 	else
-		mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
+		mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
 
 	if (pool == 0)
 		vsi = pf->main_vsi;
@@ -5652,7 +5652,7 @@  i40e_update_default_filter_setting(struct i40e_vsi *vsi)
 		mac = &f->mac_info.mac_addr;
 		rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
 				ETH_ADDR_LEN);
-		f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+		f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
 		TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 		vsi->mac_num++;
 
@@ -5660,7 +5660,7 @@  i40e_update_default_filter_setting(struct i40e_vsi *vsi)
 	}
 	rte_memcpy(&filter.mac_addr,
 		(struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
-	filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+	filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
 	return i40e_vsi_add_mac(vsi, &filter);
 }
 
@@ -6126,7 +6126,7 @@  i40e_vsi_setup(struct i40e_pf *pf,
 
 	/* MAC/VLAN configuration */
 	rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
-	filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+	filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
 
 	ret = i40e_vsi_add_mac(vsi, &filter);
 	if (ret != I40E_SUCCESS) {
@@ -6154,15 +6154,15 @@  i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
 	struct i40e_mac_filter *f;
 	void *temp;
 	struct i40e_mac_filter_info *mac_filter;
-	enum rte_mac_filter_type desired_filter;
+	enum i40e_mac_filter_type desired_filter;
 	int ret = I40E_SUCCESS;
 
 	if (on) {
 		/* Filter to match MAC and VLAN */
-		desired_filter = RTE_MACVLAN_PERFECT_MATCH;
+		desired_filter = I40E_MACVLAN_PERFECT_MATCH;
 	} else {
 		/* Filter to match only MAC */
-		desired_filter = RTE_MAC_PERFECT_MATCH;
+		desired_filter = I40E_MAC_PERFECT_MATCH;
 	}
 
 	num = vsi->mac_num;
@@ -7105,18 +7105,18 @@  i40e_add_macvlan_filters(struct i40e_vsi *vsi,
 				rte_cpu_to_le_16(filter[num + i].vlan_id);
 
 			switch (filter[num + i].filter_type) {
-			case RTE_MAC_PERFECT_MATCH:
+			case I40E_MAC_PERFECT_MATCH:
 				flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
 					I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
 				break;
-			case RTE_MACVLAN_PERFECT_MATCH:
+			case I40E_MACVLAN_PERFECT_MATCH:
 				flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
 				break;
-			case RTE_MAC_HASH_MATCH:
+			case I40E_MAC_HASH_MATCH:
 				flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
 					I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
 				break;
-			case RTE_MACVLAN_HASH_MATCH:
+			case I40E_MACVLAN_HASH_MATCH:
 				flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
 				break;
 			default:
@@ -7180,18 +7180,18 @@  i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
 				rte_cpu_to_le_16(filter[num + i].vlan_id);
 
 			switch (filter[num + i].filter_type) {
-			case RTE_MAC_PERFECT_MATCH:
+			case I40E_MAC_PERFECT_MATCH:
 				flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
 					I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
 				break;
-			case RTE_MACVLAN_PERFECT_MATCH:
+			case I40E_MACVLAN_PERFECT_MATCH:
 				flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
 				break;
-			case RTE_MAC_HASH_MATCH:
+			case I40E_MAC_HASH_MATCH:
 				flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
 					I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
 				break;
-			case RTE_MACVLAN_HASH_MATCH:
+			case I40E_MACVLAN_HASH_MATCH:
 				flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
 				break;
 			default:
@@ -7536,8 +7536,8 @@  i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
 	f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
 	if (f != NULL)
 		return I40E_SUCCESS;
-	if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
-		(mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
+	if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+		mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
 
 		/**
 		 * If vlan_num is 0, that's the first time to add mac,
@@ -7548,8 +7548,8 @@  i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
 			vsi->vlan_num = 1;
 		}
 		vlan_num = vsi->vlan_num;
-	} else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
-			(mac_filter->filter_type == RTE_MAC_HASH_MATCH))
+	} else if ((mac_filter->filter_type == I40E_MAC_PERFECT_MATCH) ||
+			(mac_filter->filter_type == I40E_MAC_HASH_MATCH))
 		vlan_num = 1;
 
 	mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
@@ -7564,8 +7564,8 @@  i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
 				ETH_ADDR_LEN);
 	}
 
-	if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
-		mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
+	if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+		mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
 		ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
 					&mac_filter->mac_addr);
 		if (ret != I40E_SUCCESS)
@@ -7602,7 +7602,7 @@  i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
 	struct i40e_mac_filter *f;
 	struct i40e_macvlan_filter *mv_f;
 	int i, vlan_num;
-	enum rte_mac_filter_type filter_type;
+	enum i40e_mac_filter_type filter_type;
 	int ret = I40E_SUCCESS;
 
 	/* Can't find it, return an error */
@@ -7612,14 +7612,14 @@  i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
 
 	vlan_num = vsi->vlan_num;
 	filter_type = f->mac_info.filter_type;
-	if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
-		filter_type == RTE_MACVLAN_HASH_MATCH) {
+	if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+		filter_type == I40E_MACVLAN_HASH_MATCH) {
 		if (vlan_num == 0) {
 			PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
 			return I40E_ERR_PARAM;
 		}
-	} else if (filter_type == RTE_MAC_PERFECT_MATCH ||
-			filter_type == RTE_MAC_HASH_MATCH)
+	} else if (filter_type == I40E_MAC_PERFECT_MATCH ||
+			filter_type == I40E_MAC_HASH_MATCH)
 		vlan_num = 1;
 
 	mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
@@ -7633,8 +7633,8 @@  i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
 		rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
 				ETH_ADDR_LEN);
 	}
-	if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
-			filter_type == RTE_MACVLAN_HASH_MATCH) {
+	if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+			filter_type == I40E_MACVLAN_HASH_MATCH) {
 		ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
 		if (ret != I40E_SUCCESS)
 			goto DONE;
@@ -7862,25 +7862,25 @@  static int
 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
 {
 	switch (filter_type) {
-	case RTE_TUNNEL_FILTER_IMAC_IVLAN:
+	case I40E_TUNNEL_FILTER_IMAC_IVLAN:
 		*flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
 		break;
-	case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
+	case I40E_TUNNEL_FILTER_IMAC_IVLAN_TENID:
 		*flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
 		break;
-	case RTE_TUNNEL_FILTER_IMAC_TENID:
+	case I40E_TUNNEL_FILTER_IMAC_TENID:
 		*flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
 		break;
-	case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
+	case I40E_TUNNEL_FILTER_OMAC_TENID_IMAC:
 		*flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
 		break;
-	case ETH_TUNNEL_FILTER_IMAC:
+	case I40E_TUNNEL_FILTER_IMAC:
 		*flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
 		break;
-	case ETH_TUNNEL_FILTER_OIP:
+	case I40E_TUNNEL_FILTER_OIP:
 		*flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
 		break;
-	case ETH_TUNNEL_FILTER_IIP:
+	case I40E_TUNNEL_FILTER_IIP:
 		*flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
 		break;
 	default:
@@ -9316,7 +9316,7 @@  i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
  */
 static int
 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
-				   struct rte_eth_hash_global_conf *g_cfg)
+				   struct i40e_hash_global_conf *g_cfg)
 {
 	struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
 	uint32_t reg;
@@ -9362,7 +9362,7 @@  i40e_get_hash_filter_global_config(struct i40e_hw *hw,
 
 static int
 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
-			      const struct rte_eth_hash_global_conf *g_cfg)
+			      const struct i40e_hash_global_conf *g_cfg)
 {
 	uint32_t i;
 	uint64_t mask0, i40e_mask = adapter->flow_types_mask;
@@ -9406,7 +9406,7 @@  i40e_hash_global_config_check(const struct i40e_adapter *adapter,
  */
 static int
 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
-				   struct rte_eth_hash_global_conf *g_cfg)
+				   struct i40e_hash_global_conf *g_cfg)
 {
 	struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
 	struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
@@ -9478,7 +9478,7 @@  i40e_set_hash_filter_global_config(struct i40e_hw *hw,
  */
 static uint64_t
 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
-		enum rte_filter_type filter)
+		enum i40e_eth_filter_type filter)
 {
 	uint64_t valid;
 
@@ -9726,7 +9726,7 @@  i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
 
 	if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
 		return 0;
-	if (filter == RTE_ETH_FILTER_HASH)
+	if (filter == I40E_ETH_FILTER_HASH)
 		valid = valid_hash_inset_table[pctype];
 	else
 		valid = valid_fdir_inset_table[pctype];
@@ -9739,7 +9739,7 @@  i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
  */
 int
 i40e_validate_input_set(enum i40e_filter_pctype pctype,
-		enum rte_filter_type filter, uint64_t inset)
+		enum i40e_eth_filter_type filter, uint64_t inset)
 {
 	uint64_t valid;
 
@@ -9817,76 +9817,76 @@  i40e_get_default_input_set(uint16_t pctype)
 static int
 i40e_parse_input_set(uint64_t *inset,
 		     enum i40e_filter_pctype pctype,
-		     enum rte_eth_input_set_field *field,
+		     enum i40e_input_set_field *field,
 		     uint16_t size)
 {
 	uint16_t i, j;
 	int ret = -EINVAL;
 
 	static const struct {
-		enum rte_eth_input_set_field field;
+		enum i40e_input_set_field field;
 		uint64_t inset;
 	} inset_convert_table[] = {
-		{RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
-		{RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
-		{RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
-		{RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
-		{RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
-		{RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
-		{RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
-		{RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
-		{RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
-		{RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
-		{RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
-		{RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
-		{RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
-		{RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
-		{RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
+		{I40E_INPUT_SET_NONE, I40E_INSET_NONE},
+		{I40E_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
+		{I40E_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
+		{I40E_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
+		{I40E_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
+		{I40E_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
+		{I40E_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
+		{I40E_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
+		{I40E_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
+		{I40E_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
+		{I40E_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
+		{I40E_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
+		{I40E_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
+		{I40E_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
+		{I40E_INPUT_SET_L3_IP6_NEXT_HEADER,
 			I40E_INSET_IPV6_NEXT_HDR},
-		{RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
+		{I40E_INPUT_SET_L3_IP6_HOP_LIMITS,
 			I40E_INSET_IPV6_HOP_LIMIT},
-		{RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
-		{RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
-		{RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
-		{RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
-		{RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
-		{RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
-		{RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
+		{I40E_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
+		{I40E_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
+		{I40E_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
+		{I40E_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
+		{I40E_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
+		{I40E_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
+		{I40E_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
 			I40E_INSET_SCTP_VT},
-		{RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
+		{I40E_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
 			I40E_INSET_TUNNEL_DMAC},
-		{RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
+		{I40E_INPUT_SET_TUNNEL_L2_INNER_VLAN,
 			I40E_INSET_VLAN_TUNNEL},
-		{RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
+		{I40E_INPUT_SET_TUNNEL_L4_UDP_KEY,
 			I40E_INSET_TUNNEL_ID},
-		{RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
-		{RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
+		{I40E_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
+		{I40E_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
 			I40E_INSET_FLEX_PAYLOAD_W1},
-		{RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
+		{I40E_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
 			I40E_INSET_FLEX_PAYLOAD_W2},
-		{RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
+		{I40E_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
 			I40E_INSET_FLEX_PAYLOAD_W3},
-		{RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
+		{I40E_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
 			I40E_INSET_FLEX_PAYLOAD_W4},
-		{RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
+		{I40E_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
 			I40E_INSET_FLEX_PAYLOAD_W5},
-		{RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
+		{I40E_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
 			I40E_INSET_FLEX_PAYLOAD_W6},
-		{RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
+		{I40E_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
 			I40E_INSET_FLEX_PAYLOAD_W7},
-		{RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
+		{I40E_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
 			I40E_INSET_FLEX_PAYLOAD_W8},
 	};
 
-	if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
+	if (!inset || !field || size > I40E_INSET_SIZE_MAX)
 		return ret;
 
 	/* Only one item allowed for default or all */
 	if (size == 1) {
-		if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
+		if (field[0] == I40E_INPUT_SET_DEFAULT) {
 			*inset = i40e_get_default_input_set(pctype);
 			return 0;
-		} else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
+		} else if (field[0] == I40E_INPUT_SET_NONE) {
 			*inset = I40E_INSET_NONE;
 			return 0;
 		}
@@ -10149,7 +10149,7 @@  i40e_filter_input_set_init(struct i40e_pf *pf)
 
 int
 i40e_hash_filter_inset_select(struct i40e_hw *hw,
-			 struct rte_eth_input_set_conf *conf)
+			 struct i40e_input_set_conf *conf)
 {
 	struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
 	enum i40e_filter_pctype pctype;
@@ -10161,8 +10161,8 @@  i40e_hash_filter_inset_select(struct i40e_hw *hw,
 		PMD_DRV_LOG(ERR, "Invalid pointer");
 		return -EFAULT;
 	}
-	if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
-	    conf->op != RTE_ETH_INPUT_SET_ADD) {
+	if (conf->op != I40E_INPUT_SET_SELECT &&
+	    conf->op != I40E_INPUT_SET_ADD) {
 		PMD_DRV_LOG(ERR, "Unsupported input set operation");
 		return -EINVAL;
 	}
@@ -10191,7 +10191,7 @@  i40e_hash_filter_inset_select(struct i40e_hw *hw,
 		return -EINVAL;
 	}
 
-	if (conf->op == RTE_ETH_INPUT_SET_ADD) {
+	if (conf->op == I40E_INPUT_SET_ADD) {
 		/* get inset value in register */
 		inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
 		inset_reg <<= I40E_32_BIT_WIDTH;
@@ -10226,7 +10226,7 @@  i40e_hash_filter_inset_select(struct i40e_hw *hw,
 
 int
 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
-			 struct rte_eth_input_set_conf *conf)
+			 struct i40e_input_set_conf *conf)
 {
 	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 	enum i40e_filter_pctype pctype;
@@ -10238,8 +10238,8 @@  i40e_fdir_filter_inset_select(struct i40e_pf *pf,
 		PMD_DRV_LOG(ERR, "Invalid pointer");
 		return -EFAULT;
 	}
-	if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
-	    conf->op != RTE_ETH_INPUT_SET_ADD) {
+	if (conf->op != I40E_INPUT_SET_SELECT &&
+	    conf->op != I40E_INPUT_SET_ADD) {
 		PMD_DRV_LOG(ERR, "Unsupported input set operation");
 		return -EINVAL;
 	}
@@ -10267,7 +10267,7 @@  i40e_fdir_filter_inset_select(struct i40e_pf *pf,
 	 * it is done by writing I40E_PRTQF_FD_FLXINSET
 	 * in i40e_set_flex_mask_on_pctype.
 	 */
-	if (conf->op == RTE_ETH_INPUT_SET_SELECT)
+	if (conf->op == I40E_INPUT_SET_SELECT)
 		inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
 	else
 		input_set |= pf->fdir.input_set[pctype];
@@ -10308,7 +10308,7 @@  i40e_fdir_filter_inset_select(struct i40e_pf *pf,
 }
 
 static int
-i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
+i40e_hash_filter_get(struct i40e_hw *hw, struct i40e_hash_filter_info *info)
 {
 	int ret = 0;
 
@@ -10318,11 +10318,11 @@  i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
 	}
 
 	switch (info->info_type) {
-	case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
+	case I40E_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
 		i40e_get_symmetric_hash_enable_per_port(hw,
 					&(info->info.enable));
 		break;
-	case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
+	case I40E_HASH_FILTER_GLOBAL_CONFIG:
 		ret = i40e_get_hash_filter_global_config(hw,
 				&(info->info.global_conf));
 		break;
@@ -10337,7 +10337,7 @@  i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
 }
 
 static int
-i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
+i40e_hash_filter_set(struct i40e_hw *hw, struct i40e_hash_filter_info *info)
 {
 	int ret = 0;
 
@@ -10347,14 +10347,14 @@  i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
 	}
 
 	switch (info->info_type) {
-	case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
+	case I40E_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
 		i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
 		break;
-	case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
+	case I40E_HASH_FILTER_GLOBAL_CONFIG:
 		ret = i40e_set_hash_filter_global_config(hw,
 				&(info->info.global_conf));
 		break;
-	case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
+	case I40E_HASH_FILTER_INPUT_SET_SELECT:
 		ret = i40e_hash_filter_inset_select(hw,
 					       &(info->info.input_set_conf));
 		break;
@@ -10383,11 +10383,11 @@  i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
 		break;
 	case RTE_ETH_FILTER_GET:
 		ret = i40e_hash_filter_get(hw,
-			(struct rte_eth_hash_filter_info *)arg);
+			(struct i40e_hash_filter_info *)arg);
 		break;
 	case RTE_ETH_FILTER_SET:
 		ret = i40e_hash_filter_set(hw,
-			(struct rte_eth_hash_filter_info *)arg);
+			(struct i40e_hash_filter_info *)arg);
 		break;
 	default:
 		PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
@@ -10401,7 +10401,7 @@  i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
 
 /* Convert ethertype filter structure */
 static int
-i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
+i40e_ethertype_filter_convert(const struct i40e_eth_ethertype_filter *input,
 			      struct i40e_ethertype_filter *filter)
 {
 	rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
@@ -10482,7 +10482,7 @@  i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
  */
 int
 i40e_ethertype_filter_set(struct i40e_pf *pf,
-			struct rte_eth_ethertype_filter *filter,
+			struct i40e_eth_ethertype_filter *filter,
 			bool add)
 {
 	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
@@ -10523,9 +10523,9 @@  i40e_ethertype_filter_set(struct i40e_pf *pf,
 		return -EINVAL;
 	}
 
-	if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
+	if (!(filter->flags & I40E_ETHTYPE_FLAGS_MAC))
 		flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
-	if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
+	if (filter->flags & I40E_ETHTYPE_FLAGS_DROP)
 		flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
 	flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
 
@@ -10587,12 +10587,12 @@  i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 	switch (filter_op) {
 	case RTE_ETH_FILTER_ADD:
 		ret = i40e_ethertype_filter_set(pf,
-			(struct rte_eth_ethertype_filter *)arg,
+			(struct i40e_eth_ethertype_filter *)arg,
 			TRUE);
 		break;
 	case RTE_ETH_FILTER_DELETE:
 		ret = i40e_ethertype_filter_set(pf,
-			(struct rte_eth_ethertype_filter *)arg,
+			(struct i40e_eth_ethertype_filter *)arg,
 			FALSE);
 		break;
 	default:
@@ -12550,9 +12550,9 @@  i40e_ethertype_filter_restore(struct i40e_pf *pf)
 
 	TAILQ_FOREACH(f, ethertype_list, rules) {
 		flags = 0;
-		if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
+		if (!(f->flags & I40E_ETHTYPE_FLAGS_MAC))
 			flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
-		if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
+		if (f->flags & I40E_ETHTYPE_FLAGS_DROP)
 			flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
 		flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
 
@@ -13271,108 +13271,108 @@  static int
 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
 {
 	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
-	struct rte_eth_input_set_conf conf;
+	struct i40e_input_set_conf conf;
 	uint64_t mask0;
 	int ret = 0;
 	uint32_t j;
 	int i;
 	static const struct {
 		uint64_t type;
-		enum rte_eth_input_set_field field;
+		enum i40e_input_set_field field;
 	} inset_match_table[] = {
 		{ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L3_SRC_IP4},
+			I40E_INPUT_SET_L3_SRC_IP4},
 		{ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
-			RTE_ETH_INPUT_SET_L3_DST_IP4},
+			I40E_INPUT_SET_L3_DST_IP4},
 		{ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
-			RTE_ETH_INPUT_SET_UNKNOWN},
+			I40E_INPUT_SET_UNKNOWN},
 		{ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
-			RTE_ETH_INPUT_SET_UNKNOWN},
+			I40E_INPUT_SET_UNKNOWN},
 
 		{ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L3_SRC_IP4},
+			I40E_INPUT_SET_L3_SRC_IP4},
 		{ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
-			RTE_ETH_INPUT_SET_L3_DST_IP4},
+			I40E_INPUT_SET_L3_DST_IP4},
 		{ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
+			I40E_INPUT_SET_L4_TCP_SRC_PORT},
 		{ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
-			RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
+			I40E_INPUT_SET_L4_TCP_DST_PORT},
 
 		{ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L3_SRC_IP4},
+			I40E_INPUT_SET_L3_SRC_IP4},
 		{ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
-			RTE_ETH_INPUT_SET_L3_DST_IP4},
+			I40E_INPUT_SET_L3_DST_IP4},
 		{ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
+			I40E_INPUT_SET_L4_UDP_SRC_PORT},
 		{ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
-			RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
+			I40E_INPUT_SET_L4_UDP_DST_PORT},
 
 		{ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L3_SRC_IP4},
+			I40E_INPUT_SET_L3_SRC_IP4},
 		{ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
-			RTE_ETH_INPUT_SET_L3_DST_IP4},
+			I40E_INPUT_SET_L3_DST_IP4},
 		{ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
+			I40E_INPUT_SET_L4_SCTP_SRC_PORT},
 		{ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
-			RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
+			I40E_INPUT_SET_L4_SCTP_DST_PORT},
 
 		{ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L3_SRC_IP4},
+			I40E_INPUT_SET_L3_SRC_IP4},
 		{ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
-			RTE_ETH_INPUT_SET_L3_DST_IP4},
+			I40E_INPUT_SET_L3_DST_IP4},
 		{ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
-			RTE_ETH_INPUT_SET_UNKNOWN},
+			I40E_INPUT_SET_UNKNOWN},
 		{ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
-			RTE_ETH_INPUT_SET_UNKNOWN},
+			I40E_INPUT_SET_UNKNOWN},
 
 		{ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L3_SRC_IP6},
+			I40E_INPUT_SET_L3_SRC_IP6},
 		{ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
-			RTE_ETH_INPUT_SET_L3_DST_IP6},
+			I40E_INPUT_SET_L3_DST_IP6},
 		{ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
-			RTE_ETH_INPUT_SET_UNKNOWN},
+			I40E_INPUT_SET_UNKNOWN},
 		{ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
-			RTE_ETH_INPUT_SET_UNKNOWN},
+			I40E_INPUT_SET_UNKNOWN},
 
 		{ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L3_SRC_IP6},
+			I40E_INPUT_SET_L3_SRC_IP6},
 		{ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
-			RTE_ETH_INPUT_SET_L3_DST_IP6},
+			I40E_INPUT_SET_L3_DST_IP6},
 		{ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
+			I40E_INPUT_SET_L4_TCP_SRC_PORT},
 		{ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
-			RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
+			I40E_INPUT_SET_L4_TCP_DST_PORT},
 
 		{ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L3_SRC_IP6},
+			I40E_INPUT_SET_L3_SRC_IP6},
 		{ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
-			RTE_ETH_INPUT_SET_L3_DST_IP6},
+			I40E_INPUT_SET_L3_DST_IP6},
 		{ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
+			I40E_INPUT_SET_L4_UDP_SRC_PORT},
 		{ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
-			RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
+			I40E_INPUT_SET_L4_UDP_DST_PORT},
 
 		{ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L3_SRC_IP6},
+			I40E_INPUT_SET_L3_SRC_IP6},
 		{ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
-			RTE_ETH_INPUT_SET_L3_DST_IP6},
+			I40E_INPUT_SET_L3_DST_IP6},
 		{ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
+			I40E_INPUT_SET_L4_SCTP_SRC_PORT},
 		{ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
-			RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
+			I40E_INPUT_SET_L4_SCTP_DST_PORT},
 
 		{ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
-			RTE_ETH_INPUT_SET_L3_SRC_IP6},
+			I40E_INPUT_SET_L3_SRC_IP6},
 		{ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
-			RTE_ETH_INPUT_SET_L3_DST_IP6},
+			I40E_INPUT_SET_L3_DST_IP6},
 		{ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
-			RTE_ETH_INPUT_SET_UNKNOWN},
+			I40E_INPUT_SET_UNKNOWN},
 		{ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
-			RTE_ETH_INPUT_SET_UNKNOWN},
+			I40E_INPUT_SET_UNKNOWN},
 	};
 
 	mask0 = types & pf->adapter->flow_types_mask;
-	conf.op = RTE_ETH_INPUT_SET_SELECT;
+	conf.op = I40E_INPUT_SET_SELECT;
 	conf.inset_size = 0;
 	for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
 		if (mask0 & (1ULL << i)) {
@@ -13385,7 +13385,7 @@  i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
 		if ((types & inset_match_table[j].type) ==
 		    inset_match_table[j].type) {
 			if (inset_match_table[j].field ==
-			    RTE_ETH_INPUT_SET_UNKNOWN)
+			    I40E_INPUT_SET_UNKNOWN)
 				return -EINVAL;
 
 			conf.field[conf.inset_size] =
@@ -13645,12 +13645,12 @@  i40e_rss_disable_hash(struct i40e_pf *pf,
 			continue;
 
 		/* Configure default input set */
-		struct rte_eth_input_set_conf input_conf = {
-			.op = RTE_ETH_INPUT_SET_SELECT,
+		struct i40e_input_set_conf input_conf = {
+			.op = I40E_INPUT_SET_SELECT,
 			.flow_type = i,
 			.inset_size = 1,
 		};
-		input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
+		input_conf.field[0] = I40E_INPUT_SET_DEFAULT;
 		i40e_hash_filter_inset_select(hw, &input_conf);
 	}
 
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 1466998aa..65395ef5b 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -266,12 +266,311 @@  enum i40e_flxpld_layer_idx {
 
 #define I40E_FDIR_PRG_PKT_CNT       128
 
+/**
+ * filter types
+ */
+enum i40e_eth_filter_type {
+	I40E_ETH_FILTER_NONE = 0,
+	I40E_ETH_FILTER_ETHERTYPE,
+	I40E_ETH_FILTER_TUNNEL,
+	I40E_ETH_FILTER_FDIR,
+	I40E_ETH_FILTER_HASH,
+	I40E_ETH_FILTER_MAX
+};
+
+/**
+ * MAC filter type
+ */
+enum i40e_mac_filter_type {
+	I40E_MAC_PERFECT_MATCH = 1, /**< exact match of MAC addr. */
+	I40E_MACVLAN_PERFECT_MATCH, /**< exact match of MAC addr and VLAN ID. */
+	I40E_MAC_HASH_MATCH,        /**< hash match of MAC addr. */
+	/** hash match of MAC addr and exact match of VLAN ID. */
+	I40E_MACVLAN_HASH_MATCH,
+};
+
+/**
+ * A structure used to define the ethertype filter entry.
+ */
+struct i40e_eth_ethertype_filter {
+	struct rte_ether_addr mac_addr;   /**< Mac address to match. */
+	uint16_t ether_type;          /**< Ether type to match */
+	uint16_t flags;               /**< Flags from I40E_ETHTYPE_FLAGS_* */
+	uint16_t queue;               /**< Queue assigned to when match*/
+};
+
+/**
+ * Define all structures for Ethertype Filter type.
+ */
+
+#define I40E_ETHTYPE_FLAGS_MAC    0x0001 /**< If set, compare mac */
+#define I40E_ETHTYPE_FLAGS_DROP   0x0002 /**< If set, drop packet when match */
+#define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
+#define I40E_FLOW_MASK_ARRAY_SIZE \
+	(RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
+
+/**
+ * filter type of tunneling packet
+ */
+#define I40E_TUNNEL_FILTER_OMAC  0x01 /**< filter by outer MAC addr */
+#define I40E_TUNNEL_FILTER_OIP   0x02 /**< filter by outer IP Addr */
+#define I40E_TUNNEL_FILTER_TENID 0x04 /**< filter by tenant ID */
+#define I40E_TUNNEL_FILTER_IMAC  0x08 /**< filter by inner MAC addr */
+#define I40E_TUNNEL_FILTER_IVLAN 0x10 /**< filter by inner VLAN ID */
+#define I40E_TUNNEL_FILTER_IIP   0x20 /**< filter by inner IP addr */
+
+#define I40E_TUNNEL_FILTER_IMAC_IVLAN (I40E_TUNNEL_FILTER_IMAC | \
+					I40E_TUNNEL_FILTER_IVLAN)
+#define I40E_TUNNEL_FILTER_IMAC_IVLAN_TENID (I40E_TUNNEL_FILTER_IMAC | \
+					I40E_TUNNEL_FILTER_IVLAN | \
+					I40E_TUNNEL_FILTER_TENID)
+#define I40E_TUNNEL_FILTER_IMAC_TENID (I40E_TUNNEL_FILTER_IMAC | \
+					I40E_TUNNEL_FILTER_TENID)
+#define I40E_TUNNEL_FILTER_OMAC_TENID_IMAC (I40E_TUNNEL_FILTER_OMAC | \
+					I40E_TUNNEL_FILTER_TENID | \
+					I40E_TUNNEL_FILTER_IMAC)
+
+#define I40E_INSET_SIZE_MAX      128 /**< Max length of input set. */
+
+/**
+ * Input set fields for Flow Director and Hash filters
+ */
+enum i40e_input_set_field {
+	I40E_INPUT_SET_UNKNOWN = 0,
+
+	/* L2 */
+	I40E_INPUT_SET_L2_SRC_MAC = 1,
+	I40E_INPUT_SET_L2_DST_MAC,
+	I40E_INPUT_SET_L2_OUTER_VLAN,
+	I40E_INPUT_SET_L2_INNER_VLAN,
+	I40E_INPUT_SET_L2_ETHERTYPE,
+
+	/* L3 */
+	I40E_INPUT_SET_L3_SRC_IP4 = 129,
+	I40E_INPUT_SET_L3_DST_IP4,
+	I40E_INPUT_SET_L3_SRC_IP6,
+	I40E_INPUT_SET_L3_DST_IP6,
+	I40E_INPUT_SET_L3_IP4_TOS,
+	I40E_INPUT_SET_L3_IP4_PROTO,
+	I40E_INPUT_SET_L3_IP6_TC,
+	I40E_INPUT_SET_L3_IP6_NEXT_HEADER,
+	I40E_INPUT_SET_L3_IP4_TTL,
+	I40E_INPUT_SET_L3_IP6_HOP_LIMITS,
+
+	/* L4 */
+	I40E_INPUT_SET_L4_UDP_SRC_PORT = 257,
+	I40E_INPUT_SET_L4_UDP_DST_PORT,
+	I40E_INPUT_SET_L4_TCP_SRC_PORT,
+	I40E_INPUT_SET_L4_TCP_DST_PORT,
+	I40E_INPUT_SET_L4_SCTP_SRC_PORT,
+	I40E_INPUT_SET_L4_SCTP_DST_PORT,
+	I40E_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
+
+	/* Tunnel */
+	I40E_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
+	I40E_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
+	I40E_INPUT_SET_TUNNEL_L2_INNER_VLAN,
+	I40E_INPUT_SET_TUNNEL_L4_UDP_KEY,
+	I40E_INPUT_SET_TUNNEL_GRE_KEY,
+
+	/* Flexible Payload */
+	I40E_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
+	I40E_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
+	I40E_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
+	I40E_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
+	I40E_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
+	I40E_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
+	I40E_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
+	I40E_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
+
+	I40E_INPUT_SET_DEFAULT = 65533,
+	I40E_INPUT_SET_NONE = 65534,
+	I40E_INPUT_SET_MAX = 65535,
+};
+
+/**
+ * Filters input set operations
+ */
+enum i40e_filter_input_set_op {
+	I40E_INPUT_SET_OP_UNKNOWN,
+	I40E_INPUT_SET_SELECT, /**< select input set */
+	I40E_INPUT_SET_ADD,    /**< add input set entry */
+	I40E_INPUT_SET_OP_MAX
+};
+
+/**
+ * A structure used to define the input set configuration for
+ * flow director and hash filters
+ */
+struct i40e_input_set_conf {
+	uint16_t flow_type;
+	uint16_t inset_size;
+	enum i40e_input_set_field field[I40E_INSET_SIZE_MAX];
+	enum i40e_filter_input_set_op op;
+};
+
+/**
+ * Flow Director filter information types.
+ */
+enum i40e_fdir_filter_info_type {
+	I40E_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
+	/** Flow Director filter input set configuration */
+	I40E_FDIR_FILTER_INPUT_SET_SELECT,
+	I40E_FDIR_FILTER_INFO_TYPE_MAX,
+};
+
+/**
+ * A structure used to set FDIR filter information, to support filter type
+ * of 'RTE_ETH_FILTER_FDIR' I40E_FDIR_FILTER_INPUT_SET_SELECT operation.
+ */
+struct i40e_fdir_filter_info {
+	enum i40e_fdir_filter_info_type info_type; /**< Information type */
+	/** Details of fdir filter information */
+	union {
+		/** Flow Director input set configuration per port */
+		struct i40e_input_set_conf input_set_conf;
+	} info;
+};
+
+/**
+ * Hash filter information types.
+ * - I40E_HASH_FILTER_SYM_HASH_ENA_PER_PORT is for getting/setting the
+ *   information/configuration of 'symmetric hash enable' per port.
+ * - I40E_HASH_FILTER_GLOBAL_CONFIG is for getting/setting the global
+ *   configurations of hash filters. Those global configurations are valid
+ *   for all ports of the same NIC.
+ * - I40E_HASH_FILTER_INPUT_SET_SELECT is for setting the global
+ *   hash input set fields
+ */
+enum i40e_hash_filter_info_type {
+	I40E_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
+	/** Symmetric hash enable per port */
+	I40E_HASH_FILTER_SYM_HASH_ENA_PER_PORT,
+	/** Configure globally for hash filter */
+	I40E_HASH_FILTER_GLOBAL_CONFIG,
+	/** Global Hash filter input set configuration */
+	I40E_HASH_FILTER_INPUT_SET_SELECT,
+	I40E_HASH_FILTER_INFO_TYPE_MAX,
+};
+
+/**
+ * A structure used to set or get global hash function configurations which
+ * include symmetric hash enable per flow type and hash function type.
+ * Each bit in sym_hash_enable_mask[] indicates if the symmetric hash of the
+ * corresponding flow type is enabled or not.
+ * Each bit in valid_bit_mask[] indicates if the corresponding bit in
+ * sym_hash_enable_mask[] is valid or not. For the configurations gotten, it
+ * also means if the flow type is supported by hardware or not.
+ */
+struct i40e_hash_global_conf {
+	enum rte_eth_hash_function hash_func; /**< Hash function type */
+	/** Bit mask for symmetric hash enable per flow type */
+	uint64_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
+	/** Bit mask indicates if the corresponding bit is valid */
+	uint64_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
+};
+
+/**
+ * A structure used to set or get hash filter information, to support filter
+ * type of 'RTE_ETH_FILTER_HASH' and its operations.
+ */
+struct i40e_hash_filter_info {
+	enum i40e_hash_filter_info_type info_type; /**< Information type */
+	/** Details of hash filter information */
+	union {
+		/** For I40E_HASH_FILTER_SYM_HASH_ENA_PER_PORT */
+		uint8_t enable;
+		/** Global configurations of hash filter */
+		struct i40e_hash_global_conf global_conf;
+		/** Global configurations of hash filter input set */
+		struct i40e_input_set_conf input_set_conf;
+	} info;
+};
+
+/**
+ * A structure used to define the input for IPV4 flow
+ */
+struct i40e_ipv4_flow {
+	uint32_t src_ip;      /**< IPv4 source address in big endian. */
+	uint32_t dst_ip;      /**< IPv4 destination address in big endian. */
+	uint8_t  tos;         /**< Type of service to match. */
+	uint8_t  ttl;         /**< Time to live to match. */
+	uint8_t  proto;       /**< Protocol, next header in big endian. */
+};
+
+/**
+ * A structure used to define the input for IPV4 UDP flow
+ */
+struct i40e_udpv4_flow {
+	struct i40e_ipv4_flow ip; /**< IPv4 fields to match. */
+	uint16_t src_port;        /**< UDP source port in big endian. */
+	uint16_t dst_port;        /**< UDP destination port in big endian. */
+};
+
+/**
+ * A structure used to define the input for IPV4 TCP flow
+ */
+struct i40e_tcpv4_flow {
+	struct i40e_ipv4_flow ip; /**< IPv4 fields to match. */
+	uint16_t src_port;        /**< TCP source port in big endian. */
+	uint16_t dst_port;        /**< TCP destination port in big endian. */
+};
+
+/**
+ * A structure used to define the input for IPV4 SCTP flow
+ */
+struct i40e_sctpv4_flow {
+	struct i40e_ipv4_flow ip; /**< IPv4 fields to match. */
+	uint16_t src_port;        /**< SCTP source port in big endian. */
+	uint16_t dst_port;        /**< SCTP destination port in big endian. */
+	uint32_t verify_tag;      /**< Verify tag in big endian */
+};
+
+/**
+ * A structure used to define the input for IPV6 flow
+ */
+struct i40e_ipv6_flow {
+	uint32_t src_ip[4];      /**< IPv6 source address in big endian. */
+	uint32_t dst_ip[4];      /**< IPv6 destination address in big endian. */
+	uint8_t  tc;             /**< Traffic class to match. */
+	uint8_t  proto;          /**< Protocol, next header to match. */
+	uint8_t  hop_limits;     /**< Hop limits to match. */
+};
+
+/**
+ * A structure used to define the input for IPV6 UDP flow
+ */
+struct i40e_udpv6_flow {
+	struct i40e_ipv6_flow ip; /**< IPv6 fields to match. */
+	uint16_t src_port;        /**< UDP source port in big endian. */
+	uint16_t dst_port;        /**< UDP destination port in big endian. */
+};
+
+/**
+ * A structure used to define the input for IPV6 TCP flow
+ */
+struct i40e_tcpv6_flow {
+	struct i40e_ipv6_flow ip; /**< IPv6 fields to match. */
+	uint16_t src_port;        /**< TCP source port to in big endian. */
+	uint16_t dst_port;        /**< TCP destination port in big endian. */
+};
+
+/**
+ * A structure used to define the input for IPV6 SCTP flow
+ */
+struct i40e_sctpv6_flow {
+	struct i40e_ipv6_flow ip; /**< IPv6 fields to match. */
+	uint16_t src_port;        /**< SCTP source port in big endian. */
+	uint16_t dst_port;        /**< SCTP destination port in big endian. */
+	uint32_t verify_tag;      /**< Verify tag in big endian. */
+};
+
 /*
  * Struct to store flow created.
  */
 struct rte_flow {
 	TAILQ_ENTRY(rte_flow) node;
-	enum rte_filter_type filter_type;
+	enum i40e_eth_filter_type filter_type;
 	void *rule;
 };
 
@@ -292,7 +591,7 @@  struct rte_pci_driver;
  * MAC filter structure
  */
 struct i40e_mac_filter_info {
-	enum rte_mac_filter_type filter_type;
+	enum i40e_mac_filter_type filter_type;
 	struct rte_ether_addr mac_addr;
 };
 
@@ -347,7 +646,7 @@  struct i40e_veb {
 /* i40e MACVLAN filter structure */
 struct i40e_macvlan_filter {
 	struct rte_ether_addr macaddr;
-	enum rte_mac_filter_type filter_type;
+	enum i40e_mac_filter_type filter_type;
 	uint16_t vlan_id;
 };
 
@@ -502,7 +801,7 @@  struct i40e_vmdq_info {
 
 /* A structure used to define the input for GTP flow */
 struct i40e_gtp_flow {
-	struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
+	struct i40e_udpv4_flow udp; /* IPv4 UDP fields to match. */
 	uint8_t msg_type;              /* Message type. */
 	uint32_t teid;                 /* TEID in big endian. */
 };
@@ -510,35 +809,35 @@  struct i40e_gtp_flow {
 /* A structure used to define the input for GTP IPV4 flow */
 struct i40e_gtp_ipv4_flow {
 	struct i40e_gtp_flow gtp;
-	struct rte_eth_ipv4_flow ip4;
+	struct i40e_ipv4_flow ip4;
 };
 
 /* A structure used to define the input for GTP IPV6 flow */
 struct i40e_gtp_ipv6_flow {
 	struct i40e_gtp_flow gtp;
-	struct rte_eth_ipv6_flow ip6;
+	struct i40e_ipv6_flow ip6;
 };
 
 /* A structure used to define the input for ESP IPV4 flow */
 struct i40e_esp_ipv4_flow {
-	struct rte_eth_ipv4_flow ipv4;
+	struct i40e_ipv4_flow ipv4;
 	uint32_t spi;	/* SPI in big endian. */
 };
 
 /* A structure used to define the input for ESP IPV6 flow */
 struct i40e_esp_ipv6_flow {
-	struct rte_eth_ipv6_flow ipv6;
+	struct i40e_ipv6_flow ipv6;
 	uint32_t spi;	/* SPI in big endian. */
 };
 /* A structure used to define the input for ESP IPV4 UDP flow */
 struct i40e_esp_ipv4_udp_flow {
-	struct rte_eth_udpv4_flow udp;
+	struct i40e_udpv4_flow udp;
 	uint32_t spi;	/* SPI in big endian. */
 };
 
 /* A structure used to define the input for ESP IPV6 UDP flow */
 struct i40e_esp_ipv6_udp_flow {
-	struct rte_eth_udpv6_flow udp;
+	struct i40e_udpv6_flow udp;
 	uint32_t spi;	/* SPI in big endian. */
 };
 
@@ -551,13 +850,13 @@  struct i40e_raw_flow {
 
 /* A structure used to define the input for L2TPv3 over IPv4 flow */
 struct i40e_ipv4_l2tpv3oip_flow {
-	struct rte_eth_ipv4_flow ip4;
+	struct i40e_ipv4_flow ip4;
 	uint32_t session_id; /* Session ID in big endian. */
 };
 
 /* A structure used to define the input for L2TPv3 over IPv6 flow */
 struct i40e_ipv6_l2tpv3oip_flow {
-	struct rte_eth_ipv6_flow ip6;
+	struct i40e_ipv6_flow ip6;
 	uint32_t session_id; /* Session ID in big endian. */
 };
 
@@ -574,14 +873,14 @@  struct i40e_l2_flow {
  */
 union i40e_fdir_flow {
 	struct i40e_l2_flow             l2_flow;
-	struct rte_eth_udpv4_flow       udp4_flow;
-	struct rte_eth_tcpv4_flow       tcp4_flow;
-	struct rte_eth_sctpv4_flow      sctp4_flow;
-	struct rte_eth_ipv4_flow        ip4_flow;
-	struct rte_eth_udpv6_flow       udp6_flow;
-	struct rte_eth_tcpv6_flow       tcp6_flow;
-	struct rte_eth_sctpv6_flow      sctp6_flow;
-	struct rte_eth_ipv6_flow        ipv6_flow;
+	struct i40e_udpv4_flow          udp4_flow;
+	struct i40e_tcpv4_flow          tcp4_flow;
+	struct i40e_sctpv4_flow         sctp4_flow;
+	struct i40e_ipv4_flow           ip4_flow;
+	struct i40e_udpv6_flow          udp6_flow;
+	struct i40e_tcpv6_flow          tcp6_flow;
+	struct i40e_sctpv6_flow         sctp6_flow;
+	struct i40e_ipv6_flow           ipv6_flow;
 	struct i40e_gtp_flow            gtp_flow;
 	struct i40e_gtp_ipv4_flow       gtp_ipv4_flow;
 	struct i40e_gtp_ipv6_flow       gtp_ipv6_flow;
@@ -602,7 +901,7 @@  enum i40e_fdir_ip_type {
 /* A structure used to contain extend input of flow */
 struct i40e_fdir_flow_ext {
 	uint16_t vlan_tci;
-	uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
+	uint8_t flexbytes[I40E_FDIR_MAX_FLEXLEN];
 	/* It is filled by the flexible payload to match. */
 	uint8_t is_vf;   /* 1 for VF, 0 for port dev */
 	uint16_t dst_id; /* VF ID, available when is_vf is 1*/
@@ -922,15 +1221,15 @@  struct i40e_tunnel_filter_conf {
 	uint32_t outer_vlan;            /**< Outer VLAN to match */
 	enum i40e_tunnel_iptype ip_type; /**< IP address type. */
 	/**
-	 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
+	 * Outer destination IP address to match if I40E_TUNNEL_FILTER_OIP
 	 * is set in filter_type, or inner destination IP address to match
-	 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
+	 * if I40E_TUNNEL_FILTER_IIP is set in filter_type.
 	 */
 	union {
 		uint32_t ipv4_addr;     /**< IPv4 address in big endian. */
 		uint32_t ipv6_addr[4];  /**< IPv6 address in big endian. */
 	} ip_addr;
-	/** Flags from ETH_TUNNEL_FILTER_XX - see above. */
+	/** Flags from I40E_TUNNEL_FILTER_XX - see above. */
 	uint16_t filter_type;
 	enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
 	enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */
@@ -1294,7 +1593,7 @@  struct i40e_vf_representor {
 extern const struct rte_flow_ops i40e_flow_ops;
 
 union i40e_filter_t {
-	struct rte_eth_ethertype_filter ethertype_filter;
+	struct i40e_eth_ethertype_filter ethertype_filter;
 	struct i40e_fdir_filter_conf fdir_filter;
 	struct rte_eth_tunnel_filter_conf tunnel_filter;
 	struct i40e_tunnel_filter_conf consistent_tunnel_filter;
@@ -1365,9 +1664,9 @@  int i40e_select_filter_input_set(struct i40e_hw *hw,
 				 enum rte_filter_type filter);
 void i40e_fdir_filter_restore(struct i40e_pf *pf);
 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
-			     struct rte_eth_input_set_conf *conf);
+			     struct i40e_input_set_conf *conf);
 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
-			     struct rte_eth_input_set_conf *conf);
+			     struct i40e_input_set_conf *conf);
 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
 				uint32_t retval, uint8_t *msg,
 				uint16_t msglen);
@@ -1393,7 +1692,7 @@  int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
 			      struct i40e_tunnel_filter_input *input);
 uint64_t i40e_get_default_input_set(uint16_t pctype);
 int i40e_ethertype_filter_set(struct i40e_pf *pf,
-			      struct rte_eth_ethertype_filter *filter,
+			      struct i40e_eth_ethertype_filter *filter,
 			      bool add);
 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 			     const struct rte_eth_fdir_filter *filter,
@@ -1427,7 +1726,7 @@  bool is_i40e_supported(struct rte_eth_dev *dev);
 bool is_i40evf_supported(struct rte_eth_dev *dev);
 
 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
-			    enum rte_filter_type filter, uint64_t inset);
+			    enum i40e_eth_filter_type filter, uint64_t inset);
 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
 				 uint8_t nb_elem);
 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c
index aa8e72949..8bcb8699c 100644
--- a/drivers/net/i40e/i40e_fdir.c
+++ b/drivers/net/i40e/i40e_fdir.c
@@ -2360,7 +2360,7 @@  i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
 		(uint32_t)hw->func_caps.fd_filters_best_effort;
 	fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
 	fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
-	for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++)
+	for (i = 1; i < I40E_FLOW_MASK_ARRAY_SIZE; i++)
 		fdir->flow_types_mask[i] = 0ULL;
 	fdir->flex_payload_unit = sizeof(uint16_t);
 	fdir->flex_bitmask_unit = sizeof(uint16_t);
@@ -2403,7 +2403,7 @@  i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
 
 static int
 i40e_fdir_filter_set(struct rte_eth_dev *dev,
-		     struct rte_eth_fdir_filter_info *info)
+		     struct i40e_fdir_filter_info *info)
 {
 	struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 	int ret = 0;
@@ -2414,7 +2414,7 @@  i40e_fdir_filter_set(struct rte_eth_dev *dev,
 	}
 
 	switch (info->info_type) {
-	case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
+	case I40E_FDIR_FILTER_INPUT_SET_SELECT:
 		ret = i40e_fdir_filter_inset_select(pf,
 				&(info->info.input_set_conf));
 		break;
@@ -2469,7 +2469,7 @@  i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
 		break;
 	case RTE_ETH_FILTER_SET:
 		ret = i40e_fdir_filter_set(dev,
-			(struct rte_eth_fdir_filter_info *)arg);
+			(struct i40e_fdir_filter_info *)arg);
 		break;
 	case RTE_ETH_FILTER_STATS:
 		i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c
index adc5da1c5..08423f00b 100644
--- a/drivers/net/i40e/i40e_flow.c
+++ b/drivers/net/i40e/i40e_flow.c
@@ -52,11 +52,11 @@  static int
 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
 				  const struct rte_flow_item *pattern,
 				  struct rte_flow_error *error,
-				  struct rte_eth_ethertype_filter *filter);
+				  struct i40e_eth_ethertype_filter *filter);
 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
 				    const struct rte_flow_action *actions,
 				    struct rte_flow_error *error,
-				    struct rte_eth_ethertype_filter *filter);
+				    struct i40e_eth_ethertype_filter *filter);
 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
 					const struct rte_flow_attr *attr,
 					const struct rte_flow_item *pattern,
@@ -144,7 +144,7 @@  const struct rte_flow_ops i40e_flow_ops = {
 };
 
 static union i40e_filter_t cons_filter;
-static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
+static enum i40e_eth_filter_type cons_filter_type = I40E_ETH_FILTER_NONE;
 /* internal pattern w/o VOID items */
 struct rte_flow_item g_items[32];
 
@@ -2041,7 +2041,7 @@  static int
 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
 				  const struct rte_flow_item *pattern,
 				  struct rte_flow_error *error,
-				  struct rte_eth_ethertype_filter *filter)
+				  struct i40e_eth_ethertype_filter *filter)
 {
 	const struct rte_flow_item *item = pattern;
 	const struct rte_flow_item_eth *eth_spec;
@@ -2093,13 +2093,13 @@  i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
 			}
 
 			/* If mask bits of destination MAC address
-			 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
+			 * are full of 1, set I40E_ETHTYPE_FLAGS_MAC.
 			 */
 			if (rte_is_broadcast_ether_addr(&eth_mask->dst)) {
 				filter->mac_addr = eth_spec->dst;
-				filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
+				filter->flags |= I40E_ETHTYPE_FLAGS_MAC;
 			} else {
-				filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
+				filter->flags &= ~I40E_ETHTYPE_FLAGS_MAC;
 			}
 			filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
 
@@ -2128,7 +2128,7 @@  static int
 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
 				 const struct rte_flow_action *actions,
 				 struct rte_flow_error *error,
-				 struct rte_eth_ethertype_filter *filter)
+				 struct i40e_eth_ethertype_filter *filter)
 {
 	struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 	const struct rte_flow_action *act;
@@ -2155,7 +2155,7 @@  i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
 			return -rte_errno;
 		}
 	} else {
-		filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
+		filter->flags |= I40E_ETHTYPE_FLAGS_DROP;
 	}
 
 	/* Check if the next non-void item is END */
@@ -2178,7 +2178,7 @@  i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
 				 struct rte_flow_error *error,
 				 union i40e_filter_t *filter)
 {
-	struct rte_eth_ethertype_filter *ethertype_filter =
+	struct i40e_eth_ethertype_filter *ethertype_filter =
 		&filter->ethertype_filter;
 	int ret;
 
@@ -2196,7 +2196,7 @@  i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
 	if (ret)
 		return ret;
 
-	cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
+	cons_filter_type = I40E_ETH_FILTER_ETHERTYPE;
 
 	return ret;
 }
@@ -2397,7 +2397,7 @@  i40e_flow_set_fdir_inset(struct i40e_pf *pf,
 	int i, num;
 
 	/* Check if the input set is valid */
-	if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
+	if (i40e_validate_input_set(pctype, I40E_ETH_FILTER_FDIR,
 				    input_set) != 0) {
 		PMD_DRV_LOG(ERR, "Invalid input set");
 		return -EINVAL;
@@ -3458,7 +3458,7 @@  i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
 	if (ret)
 		return ret;
 
-	cons_filter_type = RTE_ETH_FILTER_FDIR;
+	cons_filter_type = I40E_ETH_FILTER_FDIR;
 
 	if (pf->fdir.fdir_vsi == NULL) {
 		/* Enable fdir when fdir flow is added at first time. */
@@ -3769,19 +3769,19 @@  i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev,
 	if (ret)
 		return ret;
 
-	cons_filter_type = RTE_ETH_FILTER_TUNNEL;
+	cons_filter_type = I40E_ETH_FILTER_TUNNEL;
 
 	return ret;
 }
 
 static uint16_t i40e_supported_tunnel_filter_types[] = {
-	ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
-	ETH_TUNNEL_FILTER_IVLAN,
-	ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
-	ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
-	ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
-	ETH_TUNNEL_FILTER_IMAC,
-	ETH_TUNNEL_FILTER_IMAC,
+	I40E_TUNNEL_FILTER_IMAC | I40E_TUNNEL_FILTER_TENID |
+	I40E_TUNNEL_FILTER_IVLAN,
+	I40E_TUNNEL_FILTER_IMAC | I40E_TUNNEL_FILTER_IVLAN,
+	I40E_TUNNEL_FILTER_IMAC | I40E_TUNNEL_FILTER_TENID,
+	I40E_TUNNEL_FILTER_OMAC | I40E_TUNNEL_FILTER_TENID |
+	I40E_TUNNEL_FILTER_IMAC,
+	I40E_TUNNEL_FILTER_IMAC,
 };
 
 static int
@@ -3871,12 +3871,12 @@  i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
 					rte_memcpy(&filter->outer_mac,
 						   &eth_spec->dst,
 						   RTE_ETHER_ADDR_LEN);
-					filter_type |= ETH_TUNNEL_FILTER_OMAC;
+					filter_type |= I40E_TUNNEL_FILTER_OMAC;
 				} else {
 					rte_memcpy(&filter->inner_mac,
 						   &eth_spec->dst,
 						   RTE_ETHER_ADDR_LEN);
-					filter_type |= ETH_TUNNEL_FILTER_IMAC;
+					filter_type |= I40E_TUNNEL_FILTER_IMAC;
 				}
 			}
 			break;
@@ -3898,7 +3898,7 @@  i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
 					filter->inner_vlan =
 					      rte_be_to_cpu_16(vlan_spec->tci) &
 					      I40E_TCI_MASK;
-				filter_type |= ETH_TUNNEL_FILTER_IVLAN;
+				filter_type |= I40E_TUNNEL_FILTER_IVLAN;
 			}
 			break;
 		case RTE_FLOW_ITEM_TYPE_IPV4:
@@ -3972,7 +3972,7 @@  i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
 					   vxlan_spec->vni, 3);
 				filter->tenant_id =
 					rte_be_to_cpu_32(tenant_id_be);
-				filter_type |= ETH_TUNNEL_FILTER_TENID;
+				filter_type |= I40E_TUNNEL_FILTER_TENID;
 			}
 
 			vxlan_flag = 1;
@@ -4022,7 +4022,7 @@  i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
 	if (ret)
 		return ret;
 
-	cons_filter_type = RTE_ETH_FILTER_TUNNEL;
+	cons_filter_type = I40E_ETH_FILTER_TUNNEL;
 
 	return ret;
 }
@@ -4101,12 +4101,12 @@  i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
 					rte_memcpy(&filter->outer_mac,
 						   &eth_spec->dst,
 						   RTE_ETHER_ADDR_LEN);
-					filter_type |= ETH_TUNNEL_FILTER_OMAC;
+					filter_type |= I40E_TUNNEL_FILTER_OMAC;
 				} else {
 					rte_memcpy(&filter->inner_mac,
 						   &eth_spec->dst,
 						   RTE_ETHER_ADDR_LEN);
-					filter_type |= ETH_TUNNEL_FILTER_IMAC;
+					filter_type |= I40E_TUNNEL_FILTER_IMAC;
 				}
 			}
 
@@ -4129,7 +4129,7 @@  i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
 					filter->inner_vlan =
 					      rte_be_to_cpu_16(vlan_spec->tci) &
 					      I40E_TCI_MASK;
-				filter_type |= ETH_TUNNEL_FILTER_IVLAN;
+				filter_type |= I40E_TUNNEL_FILTER_IVLAN;
 			}
 			break;
 		case RTE_FLOW_ITEM_TYPE_IPV4:
@@ -4224,7 +4224,7 @@  i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
 					   nvgre_spec->tni, 3);
 				filter->tenant_id =
 					rte_be_to_cpu_32(tenant_id_be);
-				filter_type |= ETH_TUNNEL_FILTER_TENID;
+				filter_type |= I40E_TUNNEL_FILTER_TENID;
 			}
 
 			nvgre_flag = 1;
@@ -4274,7 +4274,7 @@  i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
 	if (ret)
 		return ret;
 
-	cons_filter_type = RTE_ETH_FILTER_TUNNEL;
+	cons_filter_type = I40E_ETH_FILTER_TUNNEL;
 
 	return ret;
 }
@@ -4431,7 +4431,7 @@  i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
 	if (ret)
 		return ret;
 
-	cons_filter_type = RTE_ETH_FILTER_TUNNEL;
+	cons_filter_type = I40E_ETH_FILTER_TUNNEL;
 
 	return ret;
 }
@@ -4571,7 +4571,7 @@  i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 	if (ret)
 		return ret;
 
-	cons_filter_type = RTE_ETH_FILTER_TUNNEL;
+	cons_filter_type = I40E_ETH_FILTER_TUNNEL;
 
 	return ret;
 }
@@ -4694,7 +4694,7 @@  i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 	if (ret)
 		return ret;
 
-	cons_filter_type = RTE_ETH_FILTER_TUNNEL;
+	cons_filter_type = I40E_ETH_FILTER_TUNNEL;
 
 	return ret;
 }
@@ -5195,7 +5195,7 @@  i40e_parse_rss_filter(struct rte_eth_dev *dev,
 	if (ret)
 		return ret;
 
-	cons_filter_type = RTE_ETH_FILTER_HASH;
+	cons_filter_type = I40E_ETH_FILTER_HASH;
 
 	return 0;
 }
@@ -5371,7 +5371,7 @@  i40e_flow_create(struct rte_eth_dev *dev,
 	if (ret < 0)
 		return NULL;
 
-	if (cons_filter_type == RTE_ETH_FILTER_FDIR) {
+	if (cons_filter_type == I40E_ETH_FILTER_FDIR) {
 		flow = i40e_fdir_entry_pool_get(fdir_info);
 		if (flow == NULL) {
 			rte_flow_error_set(error, ENOBUFS,
@@ -5391,7 +5391,7 @@  i40e_flow_create(struct rte_eth_dev *dev,
 	}
 
 	switch (cons_filter_type) {
-	case RTE_ETH_FILTER_ETHERTYPE:
+	case I40E_ETH_FILTER_ETHERTYPE:
 		ret = i40e_ethertype_filter_set(pf,
 					&cons_filter.ethertype_filter, 1);
 		if (ret)
@@ -5399,7 +5399,7 @@  i40e_flow_create(struct rte_eth_dev *dev,
 		flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
 					i40e_ethertype_filter_list);
 		break;
-	case RTE_ETH_FILTER_FDIR:
+	case I40E_ETH_FILTER_FDIR:
 		ret = i40e_flow_add_del_fdir_filter(dev,
 			       &cons_filter.fdir_filter, 1);
 		if (ret)
@@ -5407,7 +5407,7 @@  i40e_flow_create(struct rte_eth_dev *dev,
 		flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
 					i40e_fdir_filter_list);
 		break;
-	case RTE_ETH_FILTER_TUNNEL:
+	case I40E_ETH_FILTER_TUNNEL:
 		ret = i40e_dev_consistent_tunnel_filter_set(pf,
 			    &cons_filter.consistent_tunnel_filter, 1);
 		if (ret)
@@ -5415,7 +5415,7 @@  i40e_flow_create(struct rte_eth_dev *dev,
 		flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
 					i40e_tunnel_filter_list);
 		break;
-	case RTE_ETH_FILTER_HASH:
+	case I40E_ETH_FILTER_HASH:
 		ret = i40e_config_rss_filter_set(dev,
 			    &cons_filter.rss_conf);
 		if (ret)
@@ -5436,7 +5436,7 @@  i40e_flow_create(struct rte_eth_dev *dev,
 			   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
 			   "Failed to create flow.");
 
-	if (cons_filter_type != RTE_ETH_FILTER_FDIR)
+	if (cons_filter_type != I40E_ETH_FILTER_FDIR)
 		rte_free(flow);
 	else
 		i40e_fdir_entry_pool_put(fdir_info, flow);
@@ -5450,20 +5450,20 @@  i40e_flow_destroy(struct rte_eth_dev *dev,
 		  struct rte_flow_error *error)
 {
 	struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
-	enum rte_filter_type filter_type = flow->filter_type;
+	enum i40e_eth_filter_type filter_type = flow->filter_type;
 	struct i40e_fdir_info *fdir_info = &pf->fdir;
 	int ret = 0;
 
 	switch (filter_type) {
-	case RTE_ETH_FILTER_ETHERTYPE:
+	case I40E_ETH_FILTER_ETHERTYPE:
 		ret = i40e_flow_destroy_ethertype_filter(pf,
 			 (struct i40e_ethertype_filter *)flow->rule);
 		break;
-	case RTE_ETH_FILTER_TUNNEL:
+	case I40E_ETH_FILTER_TUNNEL:
 		ret = i40e_flow_destroy_tunnel_filter(pf,
 			      (struct i40e_tunnel_filter *)flow->rule);
 		break;
-	case RTE_ETH_FILTER_FDIR:
+	case I40E_ETH_FILTER_FDIR:
 		ret = i40e_flow_add_del_fdir_filter(dev,
 				&((struct i40e_fdir_filter *)flow->rule)->fdir,
 				0);
@@ -5473,7 +5473,7 @@  i40e_flow_destroy(struct rte_eth_dev *dev,
 			i40e_fdir_rx_proc_enable(dev, 0);
 		}
 		break;
-	case RTE_ETH_FILTER_HASH:
+	case I40E_ETH_FILTER_HASH:
 		ret = i40e_config_rss_filter_del(dev,
 			&((struct i40e_rss_filter *)flow->rule)->rss_filter_info);
 		break;
@@ -5486,7 +5486,7 @@  i40e_flow_destroy(struct rte_eth_dev *dev,
 
 	if (!ret) {
 		TAILQ_REMOVE(&pf->flow_list, flow, node);
-		if (filter_type == RTE_ETH_FILTER_FDIR)
+		if (filter_type == I40E_ETH_FILTER_FDIR)
 			i40e_fdir_entry_pool_put(fdir_info, flow);
 		else
 			rte_free(flow);
@@ -5510,9 +5510,9 @@  i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 	uint16_t flags = 0;
 	int ret = 0;
 
-	if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
+	if (!(filter->flags & I40E_ETHTYPE_FLAGS_MAC))
 		flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
-	if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
+	if (filter->flags & I40E_ETHTYPE_FLAGS_DROP)
 		flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
 	flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
 
@@ -5658,9 +5658,8 @@  i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
 
 		/* Delete FDIR flows in flow list. */
 		TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
-			if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
+			if (flow->filter_type == I40E_ETH_FILTER_FDIR)
 				TAILQ_REMOVE(&pf->flow_list, flow, node);
-			}
 		}
 
 		/* reset bitmap */
@@ -5710,7 +5709,7 @@  i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
 
 	/* Delete ethertype flows in flow list. */
 	TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
-		if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
+		if (flow->filter_type == I40E_ETH_FILTER_ETHERTYPE) {
 			TAILQ_REMOVE(&pf->flow_list, flow, node);
 			rte_free(flow);
 		}
@@ -5738,7 +5737,7 @@  i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
 
 	/* Delete tunnel flows in flow list. */
 	TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
-		if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
+		if (flow->filter_type == I40E_ETH_FILTER_TUNNEL) {
 			TAILQ_REMOVE(&pf->flow_list, flow, node);
 			rte_free(flow);
 		}
@@ -5761,7 +5760,7 @@  i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
 
 	/* Delete RSS flows in flow list. */
 	TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
-		if (flow->filter_type != RTE_ETH_FILTER_HASH)
+		if (flow->filter_type != I40E_ETH_FILTER_HASH)
 			continue;
 
 		if (flow->rule) {
@@ -5784,7 +5783,7 @@  i40e_flow_query(struct rte_eth_dev *dev __rte_unused,
 		void *data, struct rte_flow_error *error)
 {
 	struct i40e_rss_filter *rss_rule = (struct i40e_rss_filter *)flow->rule;
-	enum rte_filter_type filter_type = flow->filter_type;
+	enum i40e_eth_filter_type filter_type = flow->filter_type;
 	struct rte_flow_action_rss *rss_conf = data;
 
 	if (!rss_rule) {
@@ -5799,7 +5798,7 @@  i40e_flow_query(struct rte_eth_dev *dev __rte_unused,
 		case RTE_FLOW_ACTION_TYPE_VOID:
 			break;
 		case RTE_FLOW_ACTION_TYPE_RSS:
-			if (filter_type != RTE_ETH_FILTER_HASH) {
+			if (filter_type != I40E_ETH_FILTER_HASH) {
 				rte_flow_error_set(error, ENOTSUP,
 						   RTE_FLOW_ERROR_TYPE_ACTION,
 						   actions,
diff --git a/drivers/net/i40e/i40e_pf.c b/drivers/net/i40e/i40e_pf.c
index 03c2070c3..65d649b62 100644
--- a/drivers/net/i40e/i40e_pf.c
+++ b/drivers/net/i40e/i40e_pf.c
@@ -844,7 +844,7 @@  i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf *vf,
 	for (i = 0; i < addr_list->num_elements; i++) {
 		mac = (struct rte_ether_addr *)(addr_list->list[i].addr);
 		rte_memcpy(&filter.mac_addr, mac, RTE_ETHER_ADDR_LEN);
-		filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+		filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
 		if (rte_is_zero_ether_addr(mac) ||
 		    i40e_vsi_add_mac(vf->vsi, &filter)) {
 			ret = I40E_ERR_INVALID_MAC_ADDR;
diff --git a/drivers/net/i40e/rte_pmd_i40e.c b/drivers/net/i40e/rte_pmd_i40e.c
index 17938e7d3..790d04200 100644
--- a/drivers/net/i40e/rte_pmd_i40e.c
+++ b/drivers/net/i40e/rte_pmd_i40e.c
@@ -211,7 +211,7 @@  i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
 	struct i40e_mac_filter *f;
 	struct i40e_macvlan_filter *mv_f;
 	int i, vlan_num;
-	enum rte_mac_filter_type filter_type;
+	enum i40e_mac_filter_type filter_type;
 	int ret = I40E_SUCCESS;
 	void *temp;
 
@@ -219,14 +219,14 @@  i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
 	TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
 		vlan_num = vsi->vlan_num;
 		filter_type = f->mac_info.filter_type;
-		if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
-		    filter_type == RTE_MACVLAN_HASH_MATCH) {
+		if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+		    filter_type == I40E_MACVLAN_HASH_MATCH) {
 			if (vlan_num == 0) {
 				PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
 				return I40E_ERR_PARAM;
 			}
-		} else if (filter_type == RTE_MAC_PERFECT_MATCH ||
-			   filter_type == RTE_MAC_HASH_MATCH)
+		} else if (filter_type == I40E_MAC_PERFECT_MATCH ||
+			   filter_type == I40E_MAC_HASH_MATCH)
 			vlan_num = 1;
 
 		mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
@@ -241,8 +241,8 @@  i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
 					 &f->mac_info.mac_addr,
 					 ETH_ADDR_LEN);
 		}
-		if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
-		    filter_type == RTE_MACVLAN_HASH_MATCH) {
+		if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+		    filter_type == I40E_MACVLAN_HASH_MATCH) {
 			ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
 							 &f->mac_info.mac_addr);
 			if (ret != I40E_SUCCESS) {
@@ -275,8 +275,8 @@  i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
 
 	/* restore all the MACs */
 	TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
-		if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
-		    (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
+		if (f->mac_info.filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+		    f->mac_info.filter_type == I40E_MACVLAN_HASH_MATCH) {
 			/**
 			 * If vlan_num is 0, that's the first time to add mac,
 			 * set mask for vlan_id 0.
@@ -286,8 +286,8 @@  i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
 				vsi->vlan_num = 1;
 			}
 			vlan_num = vsi->vlan_num;
-		} else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
-			   (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
+		} else if (f->mac_info.filter_type == I40E_MAC_PERFECT_MATCH ||
+			   f->mac_info.filter_type == I40E_MAC_HASH_MATCH)
 			vlan_num = 1;
 
 		mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
@@ -303,8 +303,8 @@  i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
 					 ETH_ADDR_LEN);
 		}
 
-		if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
-		    f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
+		if (f->mac_info.filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+		    f->mac_info.filter_type == I40E_MACVLAN_HASH_MATCH) {
 			ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
 							 &f->mac_info.mac_addr);
 			if (ret != I40E_SUCCESS) {
@@ -768,7 +768,7 @@  int rte_pmd_i40e_set_vf_broadcast(uint16_t port, uint16_t vf_id,
 
 	if (on) {
 		rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
-		filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+		filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
 		ret = i40e_vsi_add_mac(vsi, &filter);
 	} else {
 		ret = i40e_vsi_delete_mac(vsi, &broadcast);
@@ -2388,7 +2388,7 @@  rte_pmd_i40e_add_vf_mac_addr(uint16_t port, uint16_t vf_id,
 		return -EINVAL;
 	}
 
-	mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+	mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
 	rte_ether_addr_copy(mac_addr, &mac_filter.mac_addr);
 	ret = i40e_vsi_add_mac(vsi, &mac_filter);
 	if (ret != I40E_SUCCESS) {