diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h
index ded4fb0f5..681d2d5b6 100644
--- a/drivers/net/qede/base/bcm_osal.h
+++ b/drivers/net/qede/base/bcm_osal.h
@@ -21,6 +21,7 @@
 #include <rte_ether.h>
 #include <rte_io.h>
 #include <rte_version.h>
+#include <rte_bus_pci.h>
 
 /* Forward declaration */
 struct ecore_dev;
@@ -285,11 +286,14 @@ typedef struct osal_list_t {
 	OSAL_LIST_PUSH_HEAD(new_entry, list)
 
 /* PCI config space */
-
-#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) nothing
-#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) nothing
-#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) nothing
-#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, pcie_id) 0
+#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) \
+	rte_pci_read_config((dev)->pci_dev, dst, 1, address)
+#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) \
+	rte_pci_read_config((dev)->pci_dev, dst, 2, address)
+#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) \
+	rte_pci_read_config((dev)->pci_dev, dst, 4, address)
+#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, cap) \
+	rte_pci_find_ext_capability((dev)->pci_dev, cap)
 #define OSAL_PCI_FIND_CAPABILITY(dev, pcie_id) 0
 #define OSAL_PCI_WRITE_CONFIG_WORD(dev, address, val) nothing
 #define OSAL_BAR_SIZE(dev, bar_id) 0
diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h
index 63bd7466a..750e99a8f 100644
--- a/drivers/net/qede/base/ecore.h
+++ b/drivers/net/qede/base/ecore.h
@@ -937,6 +937,9 @@ struct ecore_dev {
 	struct ecore_dbg_feature	dbg_features[DBG_FEATURE_NUM];
 	struct ecore_dbg_params		dbg_params;
 	osal_mutex_t			dbg_lock;
+
+	/* DPDK specific ecore field */
+	struct rte_pci_device		*pci_dev;
 };
 
 enum ecore_hsi_def_type {
diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 35a8394de..e895dee40 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -2787,7 +2787,7 @@ static enum _ecore_status_t ecore_hw_init_chip(struct ecore_dev *p_dev,
 		return ECORE_IO;
 	}
 
-	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_EXP_DEVCTL, &ctrl);
 	wr_mbs = (ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
 	ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0, wr_mbs);
 
@@ -5499,9 +5499,9 @@ static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
 	u32 tmp;
 
 	/* Read Vendor Id / Device Id */
-	OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_VENDOR_ID,
 				  &p_dev->vendor_id);
-	OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_DEVICE_ID,
 				  &p_dev->device_id);
 
 	/* Determine type */
diff --git a/drivers/net/qede/base/ecore_sriov.c b/drivers/net/qede/base/ecore_sriov.c
index e60257e19..dac4cbee8 100644
--- a/drivers/net/qede/base/ecore_sriov.c
+++ b/drivers/net/qede/base/ecore_sriov.c
@@ -417,15 +417,16 @@ static enum _ecore_status_t ecore_iov_pci_cfg_info(struct ecore_dev *p_dev)
 	int pos = iov->pos;
 
 	DP_VERBOSE(p_dev, ECORE_MSG_IOV, "sriov ext pos %d\n", pos);
-	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_CTRL, &iov->ctrl);
 
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_TOTAL_VF,
+				  &iov->total_vfs);
 	OSAL_PCI_READ_CONFIG_WORD(p_dev,
-				  pos + PCI_SRIOV_TOTAL_VF, &iov->total_vfs);
-	OSAL_PCI_READ_CONFIG_WORD(p_dev,
-				  pos + PCI_SRIOV_INITIAL_VF,
+				  pos + RTE_PCI_SRIOV_INITIAL_VF,
 				  &iov->initial_vfs);
 
-	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_SRIOV_NUM_VF, &iov->num_vfs);
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_NUM_VF,
+				  &iov->num_vfs);
 	if (iov->num_vfs) {
 		/* @@@TODO - in future we might want to add an OSAL here to
 		 * allow each OS to decide on its own how to act.
@@ -437,20 +438,21 @@ static enum _ecore_status_t ecore_iov_pci_cfg_info(struct ecore_dev *p_dev)
 	}
 
 	OSAL_PCI_READ_CONFIG_WORD(p_dev,
-				  pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
+				  pos + RTE_PCI_SRIOV_VF_OFFSET, &iov->offset);
 
 	OSAL_PCI_READ_CONFIG_WORD(p_dev,
-				  pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
+				  pos + RTE_PCI_SRIOV_VF_STRIDE, &iov->stride);
 
-	OSAL_PCI_READ_CONFIG_WORD(p_dev,
-				  pos + PCI_SRIOV_VF_DID, &iov->vf_device_id);
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_VF_DID,
+				  &iov->vf_device_id);
 
 	OSAL_PCI_READ_CONFIG_DWORD(p_dev,
-				   pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
+				   pos + RTE_PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
 
-	OSAL_PCI_READ_CONFIG_DWORD(p_dev, pos + PCI_SRIOV_CAP, &iov->cap);
+	OSAL_PCI_READ_CONFIG_DWORD(p_dev, pos + RTE_PCI_SRIOV_CAP, &iov->cap);
 
-	OSAL_PCI_READ_CONFIG_BYTE(p_dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
+	OSAL_PCI_READ_CONFIG_BYTE(p_dev, pos + RTE_PCI_SRIOV_FUNC_LINK,
+				  &iov->link);
 
 	DP_VERBOSE(p_dev, ECORE_MSG_IOV, "IOV info: nres %d, cap 0x%x,"
 		   "ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d,"
@@ -669,7 +671,7 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn)
 
 	/* Learn the PCI configuration */
 	pos = OSAL_PCI_FIND_EXT_CAPABILITY(p_hwfn->p_dev,
-					   PCI_EXT_CAP_ID_SRIOV);
+					   RTE_PCI_EXT_CAP_ID_SRIOV);
 	if (!pos) {
 		DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, "No PCIe IOV support\n");
 		return ECORE_SUCCESS;
diff --git a/drivers/net/qede/base/meson.build b/drivers/net/qede/base/meson.build
index 59b41c895..03a6c44f5 100644
--- a/drivers/net/qede/base/meson.build
+++ b/drivers/net/qede/base/meson.build
@@ -52,6 +52,6 @@ foreach flag: error_cflags
 endforeach
 
 base_lib = static_library('qede_base', sources,
-	dependencies: static_rte_net,
+	dependencies: [static_rte_net, static_rte_bus_pci],
 	c_args: c_args)
 base_objs = base_lib.extract_all_objects()
diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c
index aecb98261..94061ec11 100644
--- a/drivers/net/qede/qede_main.c
+++ b/drivers/net/qede/qede_main.c
@@ -37,6 +37,7 @@ static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev)
 	edev->regview = pci_dev->mem_resource[0].addr;
 	edev->doorbells = pci_dev->mem_resource[2].addr;
 	edev->db_size = pci_dev->mem_resource[2].len;
+	edev->pci_dev = pci_dev;
 }
 
 static int
diff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h
index fec51e15a..a018a6e9a 100644
--- a/lib/librte_pci/rte_pci.h
+++ b/lib/librte_pci/rte_pci.h
@@ -31,12 +31,31 @@ extern "C" {
 #define RTE_PCI_CFG_SPACE_SIZE		256
 #define RTE_PCI_CFG_SPACE_EXP_SIZE	4096
 
+#define RTE_PCI_VENDOR_ID	0x00	/* 16 bits */
+#define RTE_PCI_DEVICE_ID	0x02	/* 16 bits */
+
+/* PCI Express capability registers */
+#define RTE_PCI_EXP_DEVCTL	8	/* Device Control */
+
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 #define RTE_PCI_EXT_CAP_ID(header)	(header & 0x0000ffff)
 #define RTE_PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
 
-#define RTE_PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error Reporting */
-#define RTE_PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
+#define RTE_PCI_EXT_CAP_ID_ERR		0x01	/* Advanced Error Reporting */
+#define RTE_PCI_EXT_CAP_ID_DSN		0x03	/* Device Serial Number */
+#define RTE_PCI_EXT_CAP_ID_SRIOV	0x10	/* SR-IOV*/
+
+/* Single Root I/O Virtualization */
+#define RTE_PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
+#define RTE_PCI_SRIOV_CTRL		0x08	/* SR-IOV Control */
+#define RTE_PCI_SRIOV_INITIAL_VF	0x0c	/* Initial VFs */
+#define RTE_PCI_SRIOV_TOTAL_VF		0x0e	/* Total VFs */
+#define RTE_PCI_SRIOV_NUM_VF		0x10	/* Number of VFs */
+#define RTE_PCI_SRIOV_FUNC_LINK		0x12	/* Function Dependency Link */
+#define RTE_PCI_SRIOV_VF_OFFSET		0x14	/* First VF Offset */
+#define RTE_PCI_SRIOV_VF_STRIDE		0x16	/* Following VF Stride */
+#define RTE_PCI_SRIOV_VF_DID		0x1a	/* VF Device ID */
+#define RTE_PCI_SRIOV_SUP_PGSIZE	0x1c	/* Supported Page Sizes */
 
 /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */
 #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
