diff mbox series

[v12,3/5] common/qat: use WC store to update queue tail registers

Message ID 20200923142253.18853-4-radu.nicolau@intel.com (mailing list archive)
State Accepted, archived
Delegated to: David Marchand
Headers
Series eal: add WC store functions |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Radu Nicolau Sept. 23, 2020, 2:22 p.m. UTC 
  Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
---
 doc/guides/rel_notes/release_20_11.rst                   | 4 ++++
 drivers/common/qat/qat_adf/adf_transport_access_macros.h | 6 ++++--
 2 files changed, 8 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst
index c0307893e..3d310572c 100644
--- a/doc/guides/rel_notes/release_20_11.rst
+++ b/doc/guides/rel_notes/release_20_11.rst
@@ -89,6 +89,10 @@  New Features
 
   Updated the Intel i40e driver to use write combining stores.
 
+* **Updated Intel qat driver.**
+
+  Updated the Intel qat driver to use write combining stores.
+
 Removed Items
 -------------
 
diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h
index 1eef5513f..504ffb723 100644
--- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h
+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h
@@ -9,6 +9,8 @@ 
 /* CSR write macro */
 #define ADF_CSR_WR(csrAddr, csrOffset, val)		\
 	rte_write32(val, (((uint8_t *)csrAddr) + csrOffset))
+#define ADF_CSR_WC_WR(csrAddr, csrOffset, val)		\
+	rte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset))
 
 /* CSR read macro */
 #define ADF_CSR_RD(csrAddr, csrOffset)			\
@@ -110,10 +112,10 @@  do { \
 		ADF_RING_CSR_RING_UBASE + (ring << 2), u_base);	\
 } while (0)
 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
-	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+	ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 		ADF_RING_CSR_RING_HEAD + (ring << 2), value)
 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
-	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+	ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 		ADF_RING_CSR_RING_TAIL + (ring << 2), value)
 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
 do { \