diff --git a/examples/pipeline/Makefile b/examples/pipeline/Makefile
index 405978ced..df5176296 100644
--- a/examples/pipeline/Makefile
+++ b/examples/pipeline/Makefile
@@ -11,6 +11,8 @@ SRCS-y += main.c
 SRCS-y += obj.c
 SRCS-y += thread.c
 SRCS-y += example_l2fwd.c
+SRCS-y += example_l2fwd_macswp.c
+
 
 # Build using pkg-config variables if possible
 ifeq ($(shell pkg-config --exists libdpdk && echo 0),0)
diff --git a/examples/pipeline/cli.c b/examples/pipeline/cli.c
index a54cd79ff..9547e1b4c 100644
--- a/examples/pipeline/cli.c
+++ b/examples/pipeline/cli.c
@@ -731,6 +731,8 @@ static const char cmd_pipeline_build_help[] =
 "pipeline <pipeline_name> build <app>\n";
 
 int pipeline_setup_l2fwd(struct rte_swx_pipeline *p);
+int pipeline_setup_l2fwd_macswp(struct rte_swx_pipeline *p);
+
 static void
 cmd_pipeline_build(char **tokens,
 	uint32_t n_tokens,
@@ -757,6 +759,8 @@ cmd_pipeline_build(char **tokens,
 	app = tokens[3];
 	if (!strcmp(app, "l2fwd"))
 		status = pipeline_setup_l2fwd(p->p);
+	else if (!strcmp(app, "l2fwd_macswp"))
+		status = pipeline_setup_l2fwd_macswp(p->p);
 	else {
 		snprintf(out, out_size, MSG_ARG_INVALID, tokens[0]);
 		return;
diff --git a/examples/pipeline/example_l2fwd_macswp.c b/examples/pipeline/example_l2fwd_macswp.c
new file mode 100644
index 000000000..7922a75aa
--- /dev/null
+++ b/examples/pipeline/example_l2fwd_macswp.c
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2020 Intel Corporation
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+
+#include <rte_common.h>
+
+#include "rte_swx_pipeline.h"
+#include "rte_swx_port_ethdev.h"
+#include "rte_swx_port_source_sink.h"
+#include "rte_swx_table_em.h"
+
+#define CHECK(condition)                                                       \
+do {                                                                           \
+	if (!(condition)) {                                                    \
+		printf("Error in function %s at line %d\n",                    \
+			__FUNCTION__, __LINE__);                               \
+		return -1;                                                     \
+	}                                                                      \
+} while (0)
+
+/*
+ * Packet headers.
+ */
+static struct rte_swx_field_params ethernet_type[] = {
+	{"dst_addr", 48},
+	{"src_addr", 48},
+	{"ether_type", 16},
+};
+
+/*
+ * Packet meta-data.
+ */
+static struct rte_swx_field_params metadata_type[] = {
+	{"port", 32},
+	{"addr", 48},
+};
+
+/*
+ * Actions.
+ */
+static const char *action_macswp_instructions[] = {
+	"mov m.addr h.ethernet.dst_addr",
+	"mov h.ethernet.dst_addr h.ethernet.src_addr",
+	"mov h.ethernet.src_addr m.addr",
+	"return",
+};
+
+/*
+ * Tables.
+ */
+static const char *table_stub_actions[] = {"macswp"};
+
+static struct rte_swx_pipeline_table_params table_stub_params = {
+	/* Match. */
+	.fields = NULL,
+	.n_fields = 0,
+
+	/* Action. */
+	.action_names = table_stub_actions,
+	.n_actions = RTE_DIM(table_stub_actions),
+	.default_action_name = "macswp",
+	.default_action_data = NULL,
+	.default_action_is_const = 0,
+};
+
+/*
+ * Pipeline.
+ */
+static const char *pipeline_instructions[] = {
+	"rx m.port",
+	"extract h.ethernet",
+	"table stub",
+	"xor m.port 1",
+	"emit h.ethernet",
+	"tx m.port",
+};
+
+int
+pipeline_setup_l2fwd_macswp(struct rte_swx_pipeline *p);
+
+int
+pipeline_setup_l2fwd_macswp(struct rte_swx_pipeline *p)
+{
+	int err;
+
+	/*
+	 * Packet headers.
+	 */
+	err = rte_swx_pipeline_struct_type_register(p,
+		"ethernet_type",
+		ethernet_type,
+		RTE_DIM(ethernet_type));
+	CHECK(!err);
+
+	err = rte_swx_pipeline_packet_header_register(p,
+		"ethernet",
+		"ethernet_type");
+	CHECK(!err);
+
+	/*
+	 * Packet meta-data.
+	 */
+	err = rte_swx_pipeline_struct_type_register(p,
+		"metadata_type",
+		metadata_type,
+		RTE_DIM(metadata_type));
+	CHECK(!err);
+
+	err = rte_swx_pipeline_packet_metadata_register(p,
+		"metadata_type");
+	CHECK(!err);
+
+	/*
+	 * Actions.
+	 */
+	err = rte_swx_pipeline_action_config(p,
+		"macswp",
+		NULL,
+		action_macswp_instructions,
+		RTE_DIM(action_macswp_instructions));
+	CHECK(!err);
+
+	/*
+	 * Tables.
+	 */
+	err = rte_swx_pipeline_table_config(p,
+		"stub",
+		&table_stub_params,
+		NULL,
+		NULL,
+		0);
+	CHECK(!err);
+
+	/*
+	 * Pipeline.
+	 */
+	err = rte_swx_pipeline_instructions_config(p,
+		pipeline_instructions,
+		RTE_DIM(pipeline_instructions));
+	CHECK(!err);
+
+	return 0;
+}
diff --git a/examples/pipeline/examples/l2fwd_macswp.cli b/examples/pipeline/examples/l2fwd_macswp.cli
new file mode 100644
index 000000000..c5eb23d18
--- /dev/null
+++ b/examples/pipeline/examples/l2fwd_macswp.cli
@@ -0,0 +1,25 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2020 Intel Corporation
+
+mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
+
+link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK1 dev 0000:18:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK2 dev 0000:3b:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK3 dev 0000:3b:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+
+pipeline PIPELINE0 create 0
+
+pipeline PIPELINE0 port in 0 link LINK0 rxq 0 bsz 32
+pipeline PIPELINE0 port in 1 link LINK1 rxq 0 bsz 32
+pipeline PIPELINE0 port in 2 link LINK2 rxq 0 bsz 32
+pipeline PIPELINE0 port in 3 link LINK3 rxq 0 bsz 32
+
+pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
+pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
+pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
+pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
+
+pipeline PIPELINE0 build l2fwd_macswp
+
+thread 1 pipeline PIPELINE0 enable
diff --git a/examples/pipeline/examples/l2fwd_macswp_pcap.cli b/examples/pipeline/examples/l2fwd_macswp_pcap.cli
new file mode 100644
index 000000000..76c3071e3
--- /dev/null
+++ b/examples/pipeline/examples/l2fwd_macswp_pcap.cli
@@ -0,0 +1,20 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2020 Intel Corporation
+
+mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
+
+pipeline PIPELINE0 create 0
+
+pipeline PIPELINE0 port in 0 source MEMPOOL0 ./examples/packet.pcap
+pipeline PIPELINE0 port in 1 source MEMPOOL0 ./examples/packet.pcap
+pipeline PIPELINE0 port in 2 source MEMPOOL0 ./examples/packet.pcap
+pipeline PIPELINE0 port in 3 source MEMPOOL0 ./examples/packet.pcap
+
+pipeline PIPELINE0 port out 0 sink none
+pipeline PIPELINE0 port out 1 sink none
+pipeline PIPELINE0 port out 2 sink none
+pipeline PIPELINE0 port out 3 sink none
+
+pipeline PIPELINE0 build l2fwd_macswp
+
+thread 1 pipeline PIPELINE0 enable
diff --git a/examples/pipeline/meson.build b/examples/pipeline/meson.build
index b16de3714..b13f04e01 100644
--- a/examples/pipeline/meson.build
+++ b/examples/pipeline/meson.build
@@ -16,4 +16,5 @@ sources = files(
 	'obj.c',
 	'thread.c',
 	'example_l2fwd.c',
+	'example_l2fwd_macswp.c',
 )
