From patchwork Fri Jul 24 05:32:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 74717 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1EA90A0518; Fri, 24 Jul 2020 07:34:05 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 26E251C0C6; Fri, 24 Jul 2020 07:33:30 +0200 (CEST) Received: from mail-vs1-f99.google.com (mail-vs1-f99.google.com [209.85.217.99]) by dpdk.org (Postfix) with ESMTP id F14C91C042 for ; Fri, 24 Jul 2020 07:33:12 +0200 (CEST) Received: by mail-vs1-f99.google.com with SMTP id p25so4305109vsg.4 for ; Thu, 23 Jul 2020 22:33:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4q3mh2l0gr6Aq0iycsff8AWEZnRzGvgiBtVhYw/8h/Q=; b=Ov4iJji8BTvM4c6xQ1LrTDqR+8f5B3tPiwjaQyq87nIDKy8RF+CTM6QzXsz9qOBWac zNCXlcRqUSgyaCaQr1pFEFMAN5QQtrVni4a+9Z2XODSkp8vNiXgJ0edIZ920OeLIApJg UOEcndpDeRUpLu4iTXV5appvlHKdraOgsIQlk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4q3mh2l0gr6Aq0iycsff8AWEZnRzGvgiBtVhYw/8h/Q=; b=gV2HcDUTMBD6ycU1erp3VF0XUUKiSk2AYti7VD5s528UGU53AiZg8iEbuClOtQ6S7H xS2EntS09h7/ghN+o6XY7sVzn1S2liothDSDvyyAnmcNxhdrhWc9OeHJ001/+QbiJVNy fPO/b5ES7/b9hBVjWToa5jRf5SjCWWctlrqHdnaG1e3ET5ryk7OJAtom7RFWd1lhfBkA N95VLf33Es29ulzReE9/L9WDDYXN7PKEXw1G502vJCTBJDfPSZlg24lJEF/9BOq5vpDx b/oLceKwWyK8Q1eQ7QGtqGYm7HykRssJWYQZ3RLtyHxUtc/RlnWLkHhjBF8ehq247hxR iLtQ== X-Gm-Message-State: AOAM5307zsUkSfV5+V5IXsEajhTi7+6AnBd879NXk50Rti1UxJDDmibk QLI+pLC+GBIG4+TzC5Mbmx2KHp8auPg7LDjVHCc2o5+fmD81r9DOOBwm+8hw+ah4r6AhRKqsEWa PDhQ6cWYkAALgzcnPCP/+xRe/YEXeWVsE83vynxRehmQRfS8iUxemamrW7AxvI8qvOCtrC9NdQB lmfw== X-Google-Smtp-Source: ABdhPJyO8+mQ+jOz+9jlBRr/3UIFC28qE931ZgrEO59j+MnYbgvRZRFAHy9bDP/4tiv9YppKuseSp2VDGUQr X-Received: by 2002:a05:6102:22d2:: with SMTP id a18mr6254477vsh.0.1595568792034; Thu, 23 Jul 2020 22:33:12 -0700 (PDT) Received: from localhost.localdomain ([192.19.223.252]) by smtp-relay.gmail.com with ESMTPS id h17sm592840vsk.0.2020.07.23.22.33.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Jul 2020 22:33:12 -0700 (PDT) X-Relaying-Domain: broadcom.com From: Ajit Khaparde To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Kishore Padmanabha , Michael Baucom Date: Thu, 23 Jul 2020 22:32:20 -0700 Message-Id: <20200724053235.71069-8-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20200724053235.71069-1-ajit.khaparde@broadcom.com> References: <20200723115639.22357-1-somnath.kotur@broadcom.com> <20200724053235.71069-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 07/22] net/bnxt: update nat template X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The template is updated to support additional combinations of NAT actions. Signed-off-by: Kishore Padmanabha Reviewed-by: Michael Baucom Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 412 +++++++++++------- .../net/bnxt/tf_ulp/ulp_template_db_class.c | 16 +- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 26 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 4 +- 4 files changed, 285 insertions(+), 173 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c index 0f19e8ed1..31fe90577 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c @@ -12,80 +12,88 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { [BNXT_ULP_ACT_HID_015a] = 1, [BNXT_ULP_ACT_HID_00eb] = 2, [BNXT_ULP_ACT_HID_0043] = 3, - [BNXT_ULP_ACT_HID_01d6] = 4, - [BNXT_ULP_ACT_HID_015e] = 5, - [BNXT_ULP_ACT_HID_00ef] = 6, - [BNXT_ULP_ACT_HID_0047] = 7, - [BNXT_ULP_ACT_HID_01da] = 8, - [BNXT_ULP_ACT_HID_025b] = 9, - [BNXT_ULP_ACT_HID_01ec] = 10, - [BNXT_ULP_ACT_HID_0144] = 11, - [BNXT_ULP_ACT_HID_02d7] = 12, - [BNXT_ULP_ACT_HID_025f] = 13, - [BNXT_ULP_ACT_HID_01f0] = 14, - [BNXT_ULP_ACT_HID_0148] = 15, - [BNXT_ULP_ACT_HID_02db] = 16, - [BNXT_ULP_ACT_HID_0000] = 17, - [BNXT_ULP_ACT_HID_0002] = 18, - [BNXT_ULP_ACT_HID_0800] = 19, - [BNXT_ULP_ACT_HID_0101] = 20, - [BNXT_ULP_ACT_HID_0020] = 21, - [BNXT_ULP_ACT_HID_0901] = 22, - [BNXT_ULP_ACT_HID_0121] = 23, - [BNXT_ULP_ACT_HID_0004] = 24, - [BNXT_ULP_ACT_HID_0804] = 25, - [BNXT_ULP_ACT_HID_0105] = 26, - [BNXT_ULP_ACT_HID_0024] = 27, - [BNXT_ULP_ACT_HID_0905] = 28, - [BNXT_ULP_ACT_HID_0125] = 29, - [BNXT_ULP_ACT_HID_0001] = 30, - [BNXT_ULP_ACT_HID_0005] = 31, - [BNXT_ULP_ACT_HID_0009] = 32, - [BNXT_ULP_ACT_HID_000d] = 33, - [BNXT_ULP_ACT_HID_0021] = 34, - [BNXT_ULP_ACT_HID_0029] = 35, - [BNXT_ULP_ACT_HID_0025] = 36, - [BNXT_ULP_ACT_HID_002d] = 37, - [BNXT_ULP_ACT_HID_0801] = 38, - [BNXT_ULP_ACT_HID_0809] = 39, - [BNXT_ULP_ACT_HID_0805] = 40, - [BNXT_ULP_ACT_HID_080d] = 41, - [BNXT_ULP_ACT_HID_0c15] = 42, - [BNXT_ULP_ACT_HID_0c19] = 43, - [BNXT_ULP_ACT_HID_02f6] = 44, - [BNXT_ULP_ACT_HID_04f8] = 45, - [BNXT_ULP_ACT_HID_01df] = 46, - [BNXT_ULP_ACT_HID_05e3] = 47, - [BNXT_ULP_ACT_HID_02fa] = 48, - [BNXT_ULP_ACT_HID_04fc] = 49, - [BNXT_ULP_ACT_HID_01e3] = 50, - [BNXT_ULP_ACT_HID_05e7] = 51, - [BNXT_ULP_ACT_HID_03f7] = 52, - [BNXT_ULP_ACT_HID_05f9] = 53, - [BNXT_ULP_ACT_HID_02e0] = 54, - [BNXT_ULP_ACT_HID_06e4] = 55, - [BNXT_ULP_ACT_HID_03fb] = 56, - [BNXT_ULP_ACT_HID_05fd] = 57, - [BNXT_ULP_ACT_HID_02e4] = 58, - [BNXT_ULP_ACT_HID_06e8] = 59, - [BNXT_ULP_ACT_HID_040d] = 60, - [BNXT_ULP_ACT_HID_040f] = 61, - [BNXT_ULP_ACT_HID_0413] = 62, - [BNXT_ULP_ACT_HID_0c0d] = 63, - [BNXT_ULP_ACT_HID_0567] = 64, - [BNXT_ULP_ACT_HID_0a49] = 65, - [BNXT_ULP_ACT_HID_050e] = 66, - [BNXT_ULP_ACT_HID_0d0e] = 67, - [BNXT_ULP_ACT_HID_0668] = 68, - [BNXT_ULP_ACT_HID_0b4a] = 69, - [BNXT_ULP_ACT_HID_0411] = 70, - [BNXT_ULP_ACT_HID_056b] = 71, - [BNXT_ULP_ACT_HID_0a4d] = 72, - [BNXT_ULP_ACT_HID_0c11] = 73, - [BNXT_ULP_ACT_HID_0512] = 74, - [BNXT_ULP_ACT_HID_0d12] = 75, - [BNXT_ULP_ACT_HID_066c] = 76, - [BNXT_ULP_ACT_HID_0b4e] = 77 + [BNXT_ULP_ACT_HID_03d8] = 4, + [BNXT_ULP_ACT_HID_02c1] = 5, + [BNXT_ULP_ACT_HID_015e] = 6, + [BNXT_ULP_ACT_HID_00ef] = 7, + [BNXT_ULP_ACT_HID_0047] = 8, + [BNXT_ULP_ACT_HID_03dc] = 9, + [BNXT_ULP_ACT_HID_02c5] = 10, + [BNXT_ULP_ACT_HID_025b] = 11, + [BNXT_ULP_ACT_HID_01ec] = 12, + [BNXT_ULP_ACT_HID_0144] = 13, + [BNXT_ULP_ACT_HID_04d9] = 14, + [BNXT_ULP_ACT_HID_03c2] = 15, + [BNXT_ULP_ACT_HID_025f] = 16, + [BNXT_ULP_ACT_HID_01f0] = 17, + [BNXT_ULP_ACT_HID_0148] = 18, + [BNXT_ULP_ACT_HID_04dd] = 19, + [BNXT_ULP_ACT_HID_03c6] = 20, + [BNXT_ULP_ACT_HID_0000] = 21, + [BNXT_ULP_ACT_HID_0002] = 22, + [BNXT_ULP_ACT_HID_0800] = 23, + [BNXT_ULP_ACT_HID_0101] = 24, + [BNXT_ULP_ACT_HID_0020] = 25, + [BNXT_ULP_ACT_HID_0901] = 26, + [BNXT_ULP_ACT_HID_0121] = 27, + [BNXT_ULP_ACT_HID_0004] = 28, + [BNXT_ULP_ACT_HID_0804] = 29, + [BNXT_ULP_ACT_HID_0105] = 30, + [BNXT_ULP_ACT_HID_0024] = 31, + [BNXT_ULP_ACT_HID_0905] = 32, + [BNXT_ULP_ACT_HID_0125] = 33, + [BNXT_ULP_ACT_HID_0001] = 34, + [BNXT_ULP_ACT_HID_0005] = 35, + [BNXT_ULP_ACT_HID_0009] = 36, + [BNXT_ULP_ACT_HID_000d] = 37, + [BNXT_ULP_ACT_HID_0021] = 38, + [BNXT_ULP_ACT_HID_0029] = 39, + [BNXT_ULP_ACT_HID_0025] = 40, + [BNXT_ULP_ACT_HID_002d] = 41, + [BNXT_ULP_ACT_HID_0801] = 42, + [BNXT_ULP_ACT_HID_0809] = 43, + [BNXT_ULP_ACT_HID_0805] = 44, + [BNXT_ULP_ACT_HID_080d] = 45, + [BNXT_ULP_ACT_HID_0c15] = 46, + [BNXT_ULP_ACT_HID_0c19] = 47, + [BNXT_ULP_ACT_HID_02f6] = 48, + [BNXT_ULP_ACT_HID_04f8] = 49, + [BNXT_ULP_ACT_HID_01df] = 50, + [BNXT_ULP_ACT_HID_07e5] = 51, + [BNXT_ULP_ACT_HID_06ce] = 52, + [BNXT_ULP_ACT_HID_02fa] = 53, + [BNXT_ULP_ACT_HID_04fc] = 54, + [BNXT_ULP_ACT_HID_01e3] = 55, + [BNXT_ULP_ACT_HID_07e9] = 56, + [BNXT_ULP_ACT_HID_06d2] = 57, + [BNXT_ULP_ACT_HID_03f7] = 58, + [BNXT_ULP_ACT_HID_05f9] = 59, + [BNXT_ULP_ACT_HID_02e0] = 60, + [BNXT_ULP_ACT_HID_08e6] = 61, + [BNXT_ULP_ACT_HID_07cf] = 62, + [BNXT_ULP_ACT_HID_03fb] = 63, + [BNXT_ULP_ACT_HID_05fd] = 64, + [BNXT_ULP_ACT_HID_02e4] = 65, + [BNXT_ULP_ACT_HID_08ea] = 66, + [BNXT_ULP_ACT_HID_07d3] = 67, + [BNXT_ULP_ACT_HID_040d] = 68, + [BNXT_ULP_ACT_HID_040f] = 69, + [BNXT_ULP_ACT_HID_0413] = 70, + [BNXT_ULP_ACT_HID_0c0d] = 71, + [BNXT_ULP_ACT_HID_0567] = 72, + [BNXT_ULP_ACT_HID_0a49] = 73, + [BNXT_ULP_ACT_HID_050e] = 74, + [BNXT_ULP_ACT_HID_0d0e] = 75, + [BNXT_ULP_ACT_HID_0668] = 76, + [BNXT_ULP_ACT_HID_0b4a] = 77, + [BNXT_ULP_ACT_HID_0411] = 78, + [BNXT_ULP_ACT_HID_056b] = 79, + [BNXT_ULP_ACT_HID_0a4d] = 80, + [BNXT_ULP_ACT_HID_0c11] = 81, + [BNXT_ULP_ACT_HID_0512] = 82, + [BNXT_ULP_ACT_HID_0d12] = 83, + [BNXT_ULP_ACT_HID_066c] = 84, + [BNXT_ULP_ACT_HID_0b4e] = 85 }; struct bnxt_ulp_act_match_info ulp_act_match_list[] = { @@ -112,14 +120,25 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [4] = { - .act_hid = BNXT_ULP_ACT_HID_01d6, + .act_hid = BNXT_ULP_ACT_HID_03d8, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [5] = { + .act_hid = BNXT_ULP_ACT_HID_02c1, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [6] = { .act_hid = BNXT_ULP_ACT_HID_015e, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -127,7 +146,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [6] = { + [7] = { .act_hid = BNXT_ULP_ACT_HID_00ef, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -136,7 +155,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [7] = { + [8] = { .act_hid = BNXT_ULP_ACT_HID_0047, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -144,16 +163,28 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [8] = { - .act_hid = BNXT_ULP_ACT_HID_01da, + [9] = { + .act_hid = BNXT_ULP_ACT_HID_03dc, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [9] = { + [10] = { + .act_hid = BNXT_ULP_ACT_HID_02c5, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [11] = { .act_hid = BNXT_ULP_ACT_HID_025b, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -161,7 +192,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [10] = { + [12] = { .act_hid = BNXT_ULP_ACT_HID_01ec, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -170,7 +201,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [11] = { + [13] = { .act_hid = BNXT_ULP_ACT_HID_0144, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -178,16 +209,28 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [12] = { - .act_hid = BNXT_ULP_ACT_HID_02d7, + [14] = { + .act_hid = BNXT_ULP_ACT_HID_04d9, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [13] = { + [15] = { + .act_hid = BNXT_ULP_ACT_HID_03c2, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [16] = { .act_hid = BNXT_ULP_ACT_HID_025f, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -196,7 +239,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [14] = { + [17] = { .act_hid = BNXT_ULP_ACT_HID_01f0, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -206,7 +249,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [15] = { + [18] = { .act_hid = BNXT_ULP_ACT_HID_0148, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -215,51 +258,64 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [16] = { - .act_hid = BNXT_ULP_ACT_HID_02db, + [19] = { + .act_hid = BNXT_ULP_ACT_HID_04dd, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_ACTION_BIT_COUNT | BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, - [17] = { + [20] = { + .act_hid = BNXT_ULP_ACT_HID_03c6, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 + }, + [21] = { .act_hid = BNXT_ULP_ACT_HID_0000, .act_sig = { .bits = BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [18] = { + [22] = { .act_hid = BNXT_ULP_ACT_HID_0002, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [19] = { + [23] = { .act_hid = BNXT_ULP_ACT_HID_0800, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [20] = { + [24] = { .act_hid = BNXT_ULP_ACT_HID_0101, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [21] = { + [25] = { .act_hid = BNXT_ULP_ACT_HID_0020, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [22] = { + [26] = { .act_hid = BNXT_ULP_ACT_HID_0901, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -267,7 +323,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [23] = { + [27] = { .act_hid = BNXT_ULP_ACT_HID_0121, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_VXLAN_DECAP | @@ -275,14 +331,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [24] = { + [28] = { .act_hid = BNXT_ULP_ACT_HID_0004, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [25] = { + [29] = { .act_hid = BNXT_ULP_ACT_HID_0804, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -290,7 +346,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [26] = { + [30] = { .act_hid = BNXT_ULP_ACT_HID_0105, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -298,7 +354,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [27] = { + [31] = { .act_hid = BNXT_ULP_ACT_HID_0024, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -306,7 +362,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [28] = { + [32] = { .act_hid = BNXT_ULP_ACT_HID_0905, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -315,7 +371,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [29] = { + [33] = { .act_hid = BNXT_ULP_ACT_HID_0125, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -324,14 +380,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, - [30] = { + [34] = { .act_hid = BNXT_ULP_ACT_HID_0001, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [31] = { + [35] = { .act_hid = BNXT_ULP_ACT_HID_0005, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -339,7 +395,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [32] = { + [36] = { .act_hid = BNXT_ULP_ACT_HID_0009, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -347,7 +403,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [33] = { + [37] = { .act_hid = BNXT_ULP_ACT_HID_000d, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -356,7 +412,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [34] = { + [38] = { .act_hid = BNXT_ULP_ACT_HID_0021, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -364,7 +420,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [35] = { + [39] = { .act_hid = BNXT_ULP_ACT_HID_0029, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -373,7 +429,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [36] = { + [40] = { .act_hid = BNXT_ULP_ACT_HID_0025, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -382,7 +438,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [37] = { + [41] = { .act_hid = BNXT_ULP_ACT_HID_002d, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -392,7 +448,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [38] = { + [42] = { .act_hid = BNXT_ULP_ACT_HID_0801, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -400,7 +456,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [39] = { + [43] = { .act_hid = BNXT_ULP_ACT_HID_0809, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -409,7 +465,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [40] = { + [44] = { .act_hid = BNXT_ULP_ACT_HID_0805, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -418,7 +474,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [41] = { + [45] = { .act_hid = BNXT_ULP_ACT_HID_080d, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_MARK | @@ -428,14 +484,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [42] = { + [46] = { .act_hid = BNXT_ULP_ACT_HID_0c15, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_VXLAN_ENCAP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [43] = { + [47] = { .act_hid = BNXT_ULP_ACT_HID_0c19, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_VXLAN_ENCAP | @@ -443,14 +499,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [44] = { + [48] = { .act_hid = BNXT_ULP_ACT_HID_02f6, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [45] = { + [49] = { .act_hid = BNXT_ULP_ACT_HID_04f8, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | @@ -458,22 +514,33 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [46] = { + [50] = { .act_hid = BNXT_ULP_ACT_HID_01df, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [47] = { - .act_hid = BNXT_ULP_ACT_HID_05e3, + [51] = { + .act_hid = BNXT_ULP_ACT_HID_07e5, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [48] = { + [52] = { + .act_hid = BNXT_ULP_ACT_HID_06ce, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [53] = { .act_hid = BNXT_ULP_ACT_HID_02fa, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -481,7 +548,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [49] = { + [54] = { .act_hid = BNXT_ULP_ACT_HID_04fc, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -490,7 +557,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [50] = { + [55] = { .act_hid = BNXT_ULP_ACT_HID_01e3, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -498,16 +565,28 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [51] = { - .act_hid = BNXT_ULP_ACT_HID_05e7, + [56] = { + .act_hid = BNXT_ULP_ACT_HID_07e9, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [52] = { + [57] = { + .act_hid = BNXT_ULP_ACT_HID_06d2, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [58] = { .act_hid = BNXT_ULP_ACT_HID_03f7, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -515,7 +594,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [53] = { + [59] = { .act_hid = BNXT_ULP_ACT_HID_05f9, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -524,7 +603,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [54] = { + [60] = { .act_hid = BNXT_ULP_ACT_HID_02e0, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -532,16 +611,28 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [55] = { - .act_hid = BNXT_ULP_ACT_HID_06e4, + [61] = { + .act_hid = BNXT_ULP_ACT_HID_08e6, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [56] = { + [62] = { + .act_hid = BNXT_ULP_ACT_HID_07cf, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [63] = { .act_hid = BNXT_ULP_ACT_HID_03fb, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -550,7 +641,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [57] = { + [64] = { .act_hid = BNXT_ULP_ACT_HID_05fd, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -560,7 +651,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [58] = { + [65] = { .act_hid = BNXT_ULP_ACT_HID_02e4, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -569,30 +660,43 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [59] = { - .act_hid = BNXT_ULP_ACT_HID_06e8, + [66] = { + .act_hid = BNXT_ULP_ACT_HID_08ea, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_ACTION_BIT_COUNT | BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [60] = { + [67] = { + .act_hid = BNXT_ULP_ACT_HID_07d3, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [68] = { .act_hid = BNXT_ULP_ACT_HID_040d, .act_sig = { .bits = BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [61] = { + [69] = { .act_hid = BNXT_ULP_ACT_HID_040f, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [62] = { + [70] = { .act_hid = BNXT_ULP_ACT_HID_0413, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DROP | @@ -600,14 +704,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [63] = { + [71] = { .act_hid = BNXT_ULP_ACT_HID_0c0d, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [64] = { + [72] = { .act_hid = BNXT_ULP_ACT_HID_0567, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | @@ -616,7 +720,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [65] = { + [73] = { .act_hid = BNXT_ULP_ACT_HID_0a49, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_SET_VLAN_VID | @@ -624,14 +728,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [66] = { + [74] = { .act_hid = BNXT_ULP_ACT_HID_050e, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [67] = { + [75] = { .act_hid = BNXT_ULP_ACT_HID_0d0e, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -639,7 +743,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [68] = { + [76] = { .act_hid = BNXT_ULP_ACT_HID_0668, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -649,7 +753,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [69] = { + [77] = { .act_hid = BNXT_ULP_ACT_HID_0b4a, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_DEC_TTL | @@ -658,14 +762,14 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [70] = { + [78] = { .act_hid = BNXT_ULP_ACT_HID_0411, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [71] = { + [79] = { .act_hid = BNXT_ULP_ACT_HID_056b, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -675,7 +779,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [72] = { + [80] = { .act_hid = BNXT_ULP_ACT_HID_0a4d, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -684,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [73] = { + [81] = { .act_hid = BNXT_ULP_ACT_HID_0c11, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -692,7 +796,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [74] = { + [82] = { .act_hid = BNXT_ULP_ACT_HID_0512, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -700,7 +804,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [75] = { + [83] = { .act_hid = BNXT_ULP_ACT_HID_0d12, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -709,7 +813,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [76] = { + [84] = { .act_hid = BNXT_ULP_ACT_HID_066c, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | @@ -720,7 +824,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [77] = { + [85] = { .act_hid = BNXT_ULP_ACT_HID_0b4e, .act_sig = { .bits = BNXT_ULP_ACTION_BIT_COUNT | diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index 200a5a6cc..9de45cdc4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -17241,7 +17241,7 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 54 + .ident_bit_pos = 0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -17311,7 +17311,7 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 54 + .ident_bit_pos = 0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -17325,7 +17325,7 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 54 + .ident_bit_pos = 0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -17339,7 +17339,7 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 54 + .ident_bit_pos = 0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -17353,7 +17353,7 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 54 + .ident_bit_pos = 0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -17367,7 +17367,7 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 54 + .ident_bit_pos = 0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -17381,7 +17381,7 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 54 + .ident_bit_pos = 0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -17451,7 +17451,7 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, - .ident_bit_pos = 54 + .ident_bit_pos = 0 }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index b5deaf6c6..c9fe1bc47 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -18,7 +18,7 @@ #define BNXT_ULP_CLASS_HID_SHFTL 31 #define BNXT_ULP_CLASS_HID_MASK 2047 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 4096 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 78 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 #define BNXT_ULP_ACT_HID_HIGH_PRIME 4721 #define BNXT_ULP_ACT_HID_SHFTR 23 @@ -786,19 +786,23 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_015a = 0x015a, BNXT_ULP_ACT_HID_00eb = 0x00eb, BNXT_ULP_ACT_HID_0043 = 0x0043, - BNXT_ULP_ACT_HID_01d6 = 0x01d6, + BNXT_ULP_ACT_HID_03d8 = 0x03d8, + BNXT_ULP_ACT_HID_02c1 = 0x02c1, BNXT_ULP_ACT_HID_015e = 0x015e, BNXT_ULP_ACT_HID_00ef = 0x00ef, BNXT_ULP_ACT_HID_0047 = 0x0047, - BNXT_ULP_ACT_HID_01da = 0x01da, + BNXT_ULP_ACT_HID_03dc = 0x03dc, + BNXT_ULP_ACT_HID_02c5 = 0x02c5, BNXT_ULP_ACT_HID_025b = 0x025b, BNXT_ULP_ACT_HID_01ec = 0x01ec, BNXT_ULP_ACT_HID_0144 = 0x0144, - BNXT_ULP_ACT_HID_02d7 = 0x02d7, + BNXT_ULP_ACT_HID_04d9 = 0x04d9, + BNXT_ULP_ACT_HID_03c2 = 0x03c2, BNXT_ULP_ACT_HID_025f = 0x025f, BNXT_ULP_ACT_HID_01f0 = 0x01f0, BNXT_ULP_ACT_HID_0148 = 0x0148, - BNXT_ULP_ACT_HID_02db = 0x02db, + BNXT_ULP_ACT_HID_04dd = 0x04dd, + BNXT_ULP_ACT_HID_03c6 = 0x03c6, BNXT_ULP_ACT_HID_0000 = 0x0000, BNXT_ULP_ACT_HID_0002 = 0x0002, BNXT_ULP_ACT_HID_0800 = 0x0800, @@ -829,19 +833,23 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_02f6 = 0x02f6, BNXT_ULP_ACT_HID_04f8 = 0x04f8, BNXT_ULP_ACT_HID_01df = 0x01df, - BNXT_ULP_ACT_HID_05e3 = 0x05e3, + BNXT_ULP_ACT_HID_07e5 = 0x07e5, + BNXT_ULP_ACT_HID_06ce = 0x06ce, BNXT_ULP_ACT_HID_02fa = 0x02fa, BNXT_ULP_ACT_HID_04fc = 0x04fc, BNXT_ULP_ACT_HID_01e3 = 0x01e3, - BNXT_ULP_ACT_HID_05e7 = 0x05e7, + BNXT_ULP_ACT_HID_07e9 = 0x07e9, + BNXT_ULP_ACT_HID_06d2 = 0x06d2, BNXT_ULP_ACT_HID_03f7 = 0x03f7, BNXT_ULP_ACT_HID_05f9 = 0x05f9, BNXT_ULP_ACT_HID_02e0 = 0x02e0, - BNXT_ULP_ACT_HID_06e4 = 0x06e4, + BNXT_ULP_ACT_HID_08e6 = 0x08e6, + BNXT_ULP_ACT_HID_07cf = 0x07cf, BNXT_ULP_ACT_HID_03fb = 0x03fb, BNXT_ULP_ACT_HID_05fd = 0x05fd, BNXT_ULP_ACT_HID_02e4 = 0x02e4, - BNXT_ULP_ACT_HID_06e8 = 0x06e8, + BNXT_ULP_ACT_HID_08ea = 0x08ea, + BNXT_ULP_ACT_HID_07d3 = 0x07d3, BNXT_ULP_ACT_HID_040d = 0x040d, BNXT_ULP_ACT_HID_040f = 0x040f, BNXT_ULP_ACT_HID_0413 = 0x0413, diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index 4388a0a42..f2e2a5950 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -259,8 +259,8 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = { .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_DEC_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_dec_ttl_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_dec_ttl_act_handler }, [RTE_FLOW_ACTION_TYPE_SET_TTL] = { .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,