From patchwork Mon Jul 6 08:24:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 73200 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E9D13A00C5; Mon, 6 Jul 2020 10:30:24 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 97DE01DA12; Mon, 6 Jul 2020 10:30:09 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id A9AB61D594 for ; Mon, 6 Jul 2020 10:30:03 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 8BCA72983E5; Mon, 6 Jul 2020 01:30:02 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 8BCA72983E5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594024202; bh=ecv6vEt31cImTA1w8IGpcb9+QeaNU3FKWLzdKcsGWEE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KNJTQiG7zsIUxlcgW5ZC2QdIbYDG5mlM45hRuaTK9qQztBIJxD9h77v0WegfAOvXi JR6/h2sbVn8Am4KOA7V6Gc5SUL+3ZdxU5fYsniSHkEBQ2B7sCj7aRPWwpAeqN91NxW GPUXpsL+tPpl+UbLyIfdNsFXqUoF37dDQNZPciFc= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Mon, 6 Jul 2020 13:54:44 +0530 Message-Id: <20200706082502.26935-3-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200706082502.26935-1-somnath.kotur@broadcom.com> References: <20200706082502.26935-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 02/20] net/bnxt: add support vlan header bitmap X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Add support for the vlan headers in the matching of the flow patterns. Signed-off-by: Kishore Padmanabha Reviewed-by: Michael Baucom Signed-off-by: Somnath Kotur Signed-off-by: Venkat Duvvuru --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 20 +++--- drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 84 +++++++++++++------------- 2 files changed, 53 insertions(+), 51 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 1bf0b76..a4dbd84 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -442,43 +442,43 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, /* Update the hdr_bitmap of the vlans */ hdr_bit = ¶ms->hdr_bitmap; if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) && + !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) && !outer_vtag_num) { /* Update the vlan tag num */ outer_vtag_num++; ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_NUM, outer_vtag_num); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_PRESENT, 1); + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_OO_VLAN); } else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) && - ULP_COMP_FLD_IDX_RD(params, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT) && + !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) && outer_vtag_num == 1) { /* update the vlan tag num */ outer_vtag_num++; ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_NUM, outer_vtag_num); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_TWO_VTAGS, 1); + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_OI_VLAN); } else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) && - ULP_COMP_FLD_IDX_RD(params, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT) && ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) && !inner_vtag_num) { /* update the vlan tag num */ inner_vtag_num++; ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_NUM, inner_vtag_num); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_PRESENT, 1); + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_IO_VLAN); } else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) && - ULP_COMP_FLD_IDX_RD(params, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT) && ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) && - ULP_COMP_FLD_IDX_RD(params, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT) && inner_vtag_num == 1) { /* update the vlan tag num */ inner_vtag_num++; ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_NUM, inner_vtag_num); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_TWO_VTAGS, 1); + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_II_VLAN); } else { BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n"); return BNXT_TF_RC_ERROR; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 6955464..e13d20b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -61,18 +61,22 @@ enum bnxt_ulp_action_bit { enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000001, - BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000002, - BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000004, - BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000008, - BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000010, - BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000020, - BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000040, - BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000080, - BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000000100, - BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000000200, - BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000000400, - BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000000800, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000001000 + BNXT_ULP_HDR_BIT_OO_VLAN = 0x0000000000000002, + BNXT_ULP_HDR_BIT_OI_VLAN = 0x0000000000000004, + BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000008, + BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000010, + BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000020, + BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000040, + BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000080, + BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000100, + BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000200, + BNXT_ULP_HDR_BIT_IO_VLAN = 0x0000000000000400, + BNXT_ULP_HDR_BIT_II_VLAN = 0x0000000000000800, + BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000001000, + BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000002000, + BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000004000, + BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000008000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000000010000 }; enum bnxt_ulp_act_type { @@ -92,35 +96,33 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_NOT_USED = 0, BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 1, BNXT_ULP_CF_IDX_O_VTAG_NUM = 2, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 3, - BNXT_ULP_CF_IDX_O_TWO_VTAGS = 4, - BNXT_ULP_CF_IDX_I_VTAG_NUM = 5, - BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 6, - BNXT_ULP_CF_IDX_I_TWO_VTAGS = 7, - BNXT_ULP_CF_IDX_INCOMING_IF = 8, - BNXT_ULP_CF_IDX_DIRECTION = 9, - BNXT_ULP_CF_IDX_SVIF_FLAG = 10, - BNXT_ULP_CF_IDX_O_L3 = 11, - BNXT_ULP_CF_IDX_I_L3 = 12, - BNXT_ULP_CF_IDX_O_L4 = 13, - BNXT_ULP_CF_IDX_I_L4 = 14, - BNXT_ULP_CF_IDX_DEV_PORT_ID = 15, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 16, - BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 17, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 18, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 19, - BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 20, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 21, - BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 22, - BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 23, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 24, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 25, - BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 26, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 27, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 28, - BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 29, - BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 30, - BNXT_ULP_CF_IDX_LAST = 31 + BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3, + BNXT_ULP_CF_IDX_I_VTAG_NUM = 4, + BNXT_ULP_CF_IDX_I_TWO_VTAGS = 5, + BNXT_ULP_CF_IDX_INCOMING_IF = 6, + BNXT_ULP_CF_IDX_DIRECTION = 7, + BNXT_ULP_CF_IDX_SVIF_FLAG = 8, + BNXT_ULP_CF_IDX_O_L3 = 9, + BNXT_ULP_CF_IDX_I_L3 = 10, + BNXT_ULP_CF_IDX_O_L4 = 11, + BNXT_ULP_CF_IDX_I_L4 = 12, + BNXT_ULP_CF_IDX_DEV_PORT_ID = 13, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 14, + BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 15, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 16, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 17, + BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 18, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 19, + BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 20, + BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 21, + BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 22, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 23, + BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 24, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 25, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 26, + BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 27, + BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 28, + BNXT_ULP_CF_IDX_LAST = 29 }; enum bnxt_ulp_cond_opcode {