From patchwork Mon Jul 6 08:12:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guinan Sun X-Patchwork-Id: 73178 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7B9BBA00C5; Mon, 6 Jul 2020 10:26:02 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B179E1D95A; Mon, 6 Jul 2020 10:24:20 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 0AC1C1D94F for ; Mon, 6 Jul 2020 10:24:17 +0200 (CEST) IronPort-SDR: nKpFM24qZz1+9zho4DQ54a24pUIhmgpPiU2WkAFgrxo7Uwgyo/5GV8bweXPmzirIAnoiX4CA8H E1MqkA9/WE8w== X-IronPort-AV: E=McAfee;i="6000,8403,9673"; a="147379303" X-IronPort-AV: E=Sophos;i="5.75,318,1589266800"; d="scan'208";a="147379303" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2020 01:24:17 -0700 IronPort-SDR: XJSe7N7LZdRJ/je3i6XIi9NHxeJ8zc4tySQIKkE9la20Iqdm4XkAhDkDX/m2MjK2dG03XsCHmF ZtcBplyG2UdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,318,1589266800"; d="scan'208";a="388128913" Received: from intel.sh.intel.com ([10.239.255.48]) by fmsmga001.fm.intel.com with ESMTP; 06 Jul 2020 01:24:15 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Jeff Guo , Zhao1 Wei , Guinan Sun , Jeff Kirsher Date: Mon, 6 Jul 2020 08:12:08 +0000 Message-Id: <20200706081222.19279-14-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200706081222.19279-1-guinanx.sun@intel.com> References: <20200622064634.70941-1-guinanx.sun@intel.com> <20200706081222.19279-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH v3 13/27] net/e1000/base: add missing register defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added defines for the EEC, SHADOWINF and FLFWUPDATE registers needed for the nvmupd_validate_offset function to correctly validate the NVM update offset. Signed-off-by: Jeff Kirsher Signed-off-by: Guinan Sun --- drivers/net/e1000/base/e1000_regs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/e1000/base/e1000_regs.h b/drivers/net/e1000/base/e1000_regs.h index 9edd3c528..4af9e1746 100644 --- a/drivers/net/e1000/base/e1000_regs.h +++ b/drivers/net/e1000/base/e1000_regs.h @@ -140,6 +140,8 @@ #define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */ /* Shadow Ram Write Register - RW */ #define E1000_SRWR 0x12018 +#define E1000_EEC_REG 0x12010 + #define E1000_I210_FLMNGCTL 0x12038 #define E1000_I210_FLMNGDATA 0x1203C #define E1000_I210_FLMNGCNT 0x12040 @@ -150,6 +152,9 @@ #define E1000_I210_FLA 0x1201C +#define E1000_SHADOWINF 0x12068 +#define E1000_FLFWUPDATE 0x12108 + #define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n)) #define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */