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[1/2] doc: update bnxt nic guide

Message ID 20200701150925.63908-2-ajit.khaparde@broadcom.com (mailing list archive)
State Superseded, archived
Delegated to: Ajit Khaparde
Headers show
Series update to docs | expand


Context Check Description
ci/Intel-compilation fail Compilation issues
ci/checkpatch success coding style OK

Commit Message

Ajit Khaparde July 1, 2020, 3:09 p.m. UTC
Update documentation to indicate vector mode support on ARM CPUs.
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
 doc/guides/nics/bnxt.rst | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/doc/guides/nics/bnxt.rst b/doc/guides/nics/bnxt.rst
index a53cdad21..6ff75d0a2 100644
--- a/doc/guides/nics/bnxt.rst
+++ b/doc/guides/nics/bnxt.rst
@@ -774,9 +774,9 @@  Vector processing provides significantly improved performance over scalar
 processing (see Vector Processor, here).
 The BNXT PMD supports the vector processing using SSE (Streaming SIMD
-Extensions) instructions on x86 platforms. The BNXT vPMD (vector mode PMD) is
-currently limited to Intel/AMD CPU architecture. Support for ARM is *not*
-currently implemented.
+Extensions) instructions on x86 platforms. It also supports NEON intrinsics for
+vector processing on ARM CPUs. The BNXT vPMD (vector mode PMD) is available for
+Intel/AMD and ARM CPU architectures.
 This improved performance comes from several optimizations: