From patchwork Tue Jun 23 10:14:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Coyle, David" X-Patchwork-Id: 72018 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1DD7AA0350; Tue, 23 Jun 2020 12:36:40 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E22D41D612; Tue, 23 Jun 2020 12:36:37 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 0EA721D609 for ; Tue, 23 Jun 2020 12:36:34 +0200 (CEST) IronPort-SDR: Ed9GMuANqcP3mHcpvSLpFxNrWRsiMAbj+9qjpuHlnbjaAX79RY3JeALIOsbrdgeLZWJczu5P1B yZwNdIdhG8qA== X-IronPort-AV: E=McAfee;i="6000,8403,9660"; a="205529742" X-IronPort-AV: E=Sophos;i="5.75,271,1589266800"; d="scan'208";a="205529742" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2020 03:36:34 -0700 IronPort-SDR: UTCjqmfx8yI/53Z6nC/uNqpnXKGEziNfV5arW/cJ8451egJETmYER49Ylrk4X9WwUQDNa6EtYN IHL5Rq4p8M1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,271,1589266800"; d="scan'208";a="264755995" Received: from silpixa00399912.ir.intel.com (HELO silpixa00399912.ger.corp.intel.com) ([10.237.223.64]) by fmsmga008.fm.intel.com with ESMTP; 23 Jun 2020 03:36:29 -0700 From: David Coyle To: akhil.goyal@nxp.com, declan.doherty@intel.com, pablo.de.lara.guarch@intel.com, fiona.trahe@intel.com, roy.fan.zhang@intel.com, konstantin.ananyev@intel.com Cc: dev@dpdk.org, thomas@monjalon.net, ferruh.yigit@intel.com, brendan.ryan@intel.com, hemant.agrawal@nxp.com, anoobj@marvell.com, ruifeng.wang@arm.com, lironh@marvell.com, rnagadheeraj@marvell.com, jsrikanth@marvell.com, G.Singh@nxp.com, jianjay.zhou@huawei.com, ravi1.kumar@amd.com, bruce.richardson@intel.com, olivier.matz@6wind.com, honnappa.nagarahalli@arm.com, stephen@networkplumber.org, alexr@mellanox.com, jerinj@marvell.com, David Coyle , Mairtin o Loingsigh Date: Tue, 23 Jun 2020 11:14:18 +0100 Message-Id: <20200623101423.9215-2-david.coyle@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200623101423.9215-1-david.coyle@intel.com> References: <20200604151324.50704-1-david.coyle@intel.com> <20200623101423.9215-1-david.coyle@intel.com> Subject: [dpdk-dev] [PATCH v2 1/6] cryptodev: add security operation to crypto operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add a new security operation field to the crypto operation to allow protocol specific parameters be defined for a crypto operation. Signed-off-by: David Coyle Signed-off-by: Mairtin o Loingsigh --- lib/librte_cryptodev/rte_crypto.h | 19 +++++++++++++++++-- lib/librte_cryptodev/rte_cryptodev.c | 5 ++++- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/lib/librte_cryptodev/rte_crypto.h b/lib/librte_cryptodev/rte_crypto.h index fd5ef3a87..da0635e73 100644 --- a/lib/librte_cryptodev/rte_crypto.h +++ b/lib/librte_cryptodev/rte_crypto.h @@ -31,8 +31,10 @@ enum rte_crypto_op_type { /**< Undefined operation type */ RTE_CRYPTO_OP_TYPE_SYMMETRIC, /**< Symmetric operation */ - RTE_CRYPTO_OP_TYPE_ASYMMETRIC + RTE_CRYPTO_OP_TYPE_ASYMMETRIC, /**< Asymmetric operation */ + RTE_CRYPTO_OP_TYPE_SECURITY + /**< Security operation */ }; /** Status of crypto operation */ @@ -121,9 +123,16 @@ struct rte_crypto_op { struct rte_crypto_asym_op asym[0]; /**< Asymmetric operation parameters */ + uint8_t security[0]; + /**< Security operation parameters + * - Must be accessed through a rte_security_op pointer + */ }; /**< operation specific parameters */ }; +/** Maximum size of security crypto op */ +#define RTE_CRYPTO_OP_SECURITY_MAX_SZ (88U) + /** * Reset the fields of a crypto operation to their default values. * @@ -143,7 +152,10 @@ __rte_crypto_op_reset(struct rte_crypto_op *op, enum rte_crypto_op_type type) break; case RTE_CRYPTO_OP_TYPE_ASYMMETRIC: memset(op->asym, 0, sizeof(struct rte_crypto_asym_op)); - break; + break; + case RTE_CRYPTO_OP_TYPE_SECURITY: + memset(op->security, 0, RTE_CRYPTO_OP_SECURITY_MAX_SZ); + break; case RTE_CRYPTO_OP_TYPE_UNDEFINED: default: break; @@ -317,6 +329,9 @@ __rte_crypto_op_get_priv_data(struct rte_crypto_op *op, uint32_t size) if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) return (void *)((uint8_t *)(op + 1) + sizeof(struct rte_crypto_asym_op)); + if (op->type == RTE_CRYPTO_OP_TYPE_SECURITY) + return (void *)((uint8_t *)(op + 1) + + RTE_CRYPTO_OP_SECURITY_MAX_SZ); } } diff --git a/lib/librte_cryptodev/rte_cryptodev.c b/lib/librte_cryptodev/rte_cryptodev.c index e37b83afd..41128f437 100644 --- a/lib/librte_cryptodev/rte_cryptodev.c +++ b/lib/librte_cryptodev/rte_cryptodev.c @@ -1871,9 +1871,12 @@ rte_crypto_op_pool_create(const char *name, enum rte_crypto_op_type type, elt_size += sizeof(struct rte_crypto_sym_op); } else if (type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { elt_size += sizeof(struct rte_crypto_asym_op); + } else if (type == RTE_CRYPTO_OP_TYPE_SECURITY) { + elt_size += RTE_CRYPTO_OP_SECURITY_MAX_SZ; } else if (type == RTE_CRYPTO_OP_TYPE_UNDEFINED) { elt_size += RTE_MAX(sizeof(struct rte_crypto_sym_op), - sizeof(struct rte_crypto_asym_op)); + RTE_MAX(sizeof(struct rte_crypto_asym_op), + RTE_CRYPTO_OP_SECURITY_MAX_SZ)); } else { CDEV_LOG_ERR("Invalid op_type\n"); return NULL;