From patchwork Mon Jun 22 06:46:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guinan Sun X-Patchwork-Id: 71925 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E74ABA0350; Mon, 22 Jun 2020 09:16:08 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2ABD71D5EC; Mon, 22 Jun 2020 09:07:14 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 1AA7A1C1AA for ; Mon, 22 Jun 2020 09:07:08 +0200 (CEST) IronPort-SDR: afa1VWmtdXERfbOpFTiT96/hIdC2FgALMUyWIWxrGpt5l6qe359rCXIyco49gyyL71luB3YnZZ SFjvxjR7M5hg== X-IronPort-AV: E=McAfee;i="6000,8403,9659"; a="131070867" X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="131070867" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2020 00:07:08 -0700 IronPort-SDR: rwTz7mqVZx5fcDwE17cXSyscpmSDMkeu86CfLL/vMLCsKe3XsADQleFAEADI7o2pmVtGqMpUXh 9oy7fOPJPiuA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="384409254" Received: from dpdk.sh.intel.com ([10.239.255.83]) by fmsmga001.fm.intel.com with ESMTP; 22 Jun 2020 00:07:07 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Jeff Guo , Zhao1 Wei , Guinan Sun , Sasha Neftin Date: Mon, 22 Jun 2020 06:46:22 +0000 Message-Id: <20200622064634.70941-59-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200622064634.70941-1-guinanx.sun@intel.com> References: <20200622064634.70941-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH 58/70] net/e1000/base: add PHY power management control X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" PHY power management control should provide a reliable and accurate indication of PHY reset completion and decrease the delay time after a PHY reset. Signed-off-by: Sasha Neftin Signed-off-by: Guinan Sun --- drivers/net/e1000/base/e1000_defines.h | 4 ++++ drivers/net/e1000/base/e1000_phy.c | 12 +++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/net/e1000/base/e1000_defines.h b/drivers/net/e1000/base/e1000_defines.h index 00afdaa25..effd04dfd 100644 --- a/drivers/net/e1000/base/e1000_defines.h +++ b/drivers/net/e1000/base/e1000_defines.h @@ -1100,8 +1100,12 @@ #define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */ #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */ #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */ + #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ + +#define E1000_PHY_RST_COMP 0x0100 /* Internal PHY reset completion */ + /* NVM Control */ #define E1000_EECD_SK 0x00000001 /* NVM Clock */ #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ diff --git a/drivers/net/e1000/base/e1000_phy.c b/drivers/net/e1000/base/e1000_phy.c index b9d8739ee..712ec1269 100644 --- a/drivers/net/e1000/base/e1000_phy.c +++ b/drivers/net/e1000/base/e1000_phy.c @@ -2877,6 +2877,7 @@ s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; + u32 phpm = 0, timeout = 10000; s32 ret_val; u32 ctrl; @@ -2892,6 +2893,7 @@ s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) if (ret_val) return ret_val; + phpm = E1000_READ_REG(hw, E1000_I225_PHPM); ctrl = E1000_READ_REG(hw, E1000_CTRL); E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); E1000_WRITE_FLUSH(hw); @@ -2901,7 +2903,15 @@ s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_CTRL, ctrl); E1000_WRITE_FLUSH(hw); - usec_delay(150); + /* SW should guarantee 100us for the completion of the PHY reset */ + usec_delay(100); + do { + phpm = E1000_READ_REG(hw, E1000_I225_PHPM); + timeout--; + usec_delay(1); + } while (!(phpm & E1000_PHY_RST_COMP) && timeout); + + usec_delay(100); phy->ops.release(hw);