From patchwork Mon Jun 22 06:45:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guinan Sun X-Patchwork-Id: 71889 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8CE65A0350; Mon, 22 Jun 2020 09:09:21 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2D9011D405; Mon, 22 Jun 2020 09:05:59 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 704371D40F for ; Mon, 22 Jun 2020 09:05:56 +0200 (CEST) IronPort-SDR: EBa2EZA2xI+3fpT9ZSWxBi2Gua8sssZSXxicj6K6qvdxhbi8UXrNMgXc879Oc+XEzff1RWUJxy /nSkZodUTnoA== X-IronPort-AV: E=McAfee;i="6000,8403,9659"; a="141944798" X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="141944798" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2020 00:05:56 -0700 IronPort-SDR: HCqumwkY+infoQfrcO8f0Oyt9Nfr3dq+jEjFdwtF/zyre8sP3V7TomQJ59dzDCBQkCaZR7AToj mK6ehFTjm6NA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="384408911" Received: from dpdk.sh.intel.com ([10.239.255.83]) by fmsmga001.fm.intel.com with ESMTP; 22 Jun 2020 00:05:54 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Jeff Guo , Zhao1 Wei , Guinan Sun , Lotem Leder Date: Mon, 22 Jun 2020 06:45:46 +0000 Message-Id: <20200622064634.70941-23-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200622064634.70941-1-guinanx.sun@intel.com> References: <20200622064634.70941-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH 22/70] net/e1000/base: add EEE support for i225 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds function e1000_set_eee_i225 which support EEE advertisement for 2.5G. Signed-off-by: Lotem Leder Signed-off-by: Guinan Sun --- drivers/net/e1000/base/e1000_defines.h | 1 + drivers/net/e1000/base/e1000_i225.c | 70 ++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/drivers/net/e1000/base/e1000_defines.h b/drivers/net/e1000/base/e1000_defines.h index 141cdcc60..03006cd6e 100644 --- a/drivers/net/e1000/base/e1000_defines.h +++ b/drivers/net/e1000/base/e1000_defines.h @@ -821,6 +821,7 @@ #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ /* I350 EEE defines */ +#define E1000_IPCNFG_EEE_2_5G_AN 0x00000010 /* IPCNFG EEE Ena 2.5G AN */ #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ diff --git a/drivers/net/e1000/base/e1000_i225.c b/drivers/net/e1000/base/e1000_i225.c index dbebb6fa3..87ccf6d9c 100644 --- a/drivers/net/e1000/base/e1000_i225.c +++ b/drivers/net/e1000/base/e1000_i225.c @@ -1205,3 +1205,73 @@ s32 e1000_set_d3_lplu_state_i225(struct e1000_hw *hw, bool active) E1000_WRITE_REG(hw, E1000_I225_PHPM, data); return E1000_SUCCESS; } + + +/** + * e1000_set_eee_i225 - Enable/disable EEE support + * @hw: pointer to the HW structure + * @adv2p5G: boolean flag enabling 2.5G EEE advertisement + * @adv1G: boolean flag enabling 1G EEE advertisement + * @adv100M: boolean flag enabling 100M EEE advertisement + * + * Enable/disable EEE based on setting in dev_spec structure. + * + **/ +s32 e1000_set_eee_i225(struct e1000_hw *hw, bool adv2p5G, bool adv1G, + bool adv100M) +{ + u32 ipcnfg, eeer; + + DEBUGFUNC("e1000_set_eee_i225"); + + if (hw->mac.type != e1000_i225 || + hw->phy.media_type != e1000_media_type_copper) + goto out; + ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); + eeer = E1000_READ_REG(hw, E1000_EEER); + + /* enable or disable per user setting */ + if (!(hw->dev_spec._82575.eee_disable)) { + u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); + + if (adv100M) + ipcnfg |= E1000_IPCNFG_EEE_100M_AN; + else + ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN; + + if (adv1G) + ipcnfg |= E1000_IPCNFG_EEE_1G_AN; + else + ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN; + + if (adv2p5G) + ipcnfg |= E1000_IPCNFG_EEE_2_5G_AN; + else + ipcnfg &= ~E1000_IPCNFG_EEE_2_5G_AN; + + eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | + E1000_EEER_LPI_FC); + +#ifndef EXTERNAL_RELEASE + /* + * This bit is supposed to be cleared by the NVM. However, older + * NVMs may not have done this (Springville HW HSD #359296). + */ +#endif /* EXTERNAL_RELEASE */ + /* This bit should not be set in normal operation. */ + if (eee_su & E1000_EEE_SU_LPI_CLK_STP) + DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); + } else { + ipcnfg &= ~(E1000_IPCNFG_EEE_2_5G_AN | E1000_IPCNFG_EEE_1G_AN | + E1000_IPCNFG_EEE_100M_AN); + eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | + E1000_EEER_LPI_FC); + } + E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); + E1000_WRITE_REG(hw, E1000_EEER, eeer); + E1000_READ_REG(hw, E1000_IPCNFG); + E1000_READ_REG(hw, E1000_EEER); +out: + + return E1000_SUCCESS; +}