From patchwork Fri Jun 12 03:23:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guinan Sun X-Patchwork-Id: 71331 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 98F4AA00BE; Fri, 12 Jun 2020 05:47:09 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 57DED1BEAC; Fri, 12 Jun 2020 05:46:20 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 85E061BE7D for ; Fri, 12 Jun 2020 05:46:16 +0200 (CEST) IronPort-SDR: P8pYb61yM/mC+3AEK+H9ZHCVAPkXrbrTtC3Eth1r7auJ4dxfWzziLVmPfOQAI9HrGZ6oRdRnFy XK28LFOKdpsQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2020 20:46:16 -0700 IronPort-SDR: 31+9sIPSrfRmYxzGZsLylslVUp5mM/3dScGXT7I6C5uIj9JqxxLyOl1/4DOELbYjyljP+sZROz PRJT6YjVty8Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,501,1583222400"; d="scan'208";a="289759506" Received: from intel.sh.intel.com ([10.239.255.18]) by orsmga002.jf.intel.com with ESMTP; 11 Jun 2020 20:46:14 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Guinan Sun , Piotr Skajewski Date: Fri, 12 Jun 2020 03:23:56 +0000 Message-Id: <20200612032410.20864-8-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200612032410.20864-1-guinanx.sun@intel.com> References: <20200612032410.20864-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH 07/21] net/ixgbe/base: added register definitions for NVM update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added additional register for X550 and above device family. Signed-off-by: Piotr Skajewski Signed-off-by: Guinan Sun --- drivers/net/ixgbe/base/ixgbe_type.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h index c1ee4c680..9838e0643 100644 --- a/drivers/net/ixgbe/base/ixgbe_type.h +++ b/drivers/net/ixgbe/base/ixgbe_type.h @@ -1086,8 +1086,10 @@ struct ixgbe_dmac_config { #define IXGBE_HSMC0R 0x15F04 #define IXGBE_HSMC1R 0x15F08 #define IXGBE_SWSR 0x15F10 +#define IXGBE_FWRESETCNT 0x15F40 #define IXGBE_HFDR 0x15FE8 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ +#define IXGBE_FLEX_MNG_PTR(_i) (IXGBE_FLEX_MNG + ((_i) * 4)) #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ /* Driver sets this bit when done to put command in RAM */