From patchwork Fri Jun 12 03:23:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guinan Sun X-Patchwork-Id: 71329 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3D570A00BE; Fri, 12 Jun 2020 05:46:49 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 593D41BE88; Fri, 12 Jun 2020 05:46:17 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id A859614581 for ; Fri, 12 Jun 2020 05:46:12 +0200 (CEST) IronPort-SDR: PPp8XidL0JeZ2QXPNKCCoHASqbLUjDI8bB6kZDv4DtxlVH34kvroHbra8slNB5rHJ3sB99fEUH GFlPJe79gwww== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2020 20:46:12 -0700 IronPort-SDR: 59lgZdZC4f1r7I1LsNtXPeN3HBELl2eiAXcnBMZRioQOg4U7jkR7Ig5t/XWXS3/hCR64QYqddC VlQQ2nJLw4fw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,501,1583222400"; d="scan'208";a="289759488" Received: from intel.sh.intel.com ([10.239.255.18]) by orsmga002.jf.intel.com with ESMTP; 11 Jun 2020 20:46:10 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Guinan Sun , Piotr Skajewski Date: Fri, 12 Jun 2020 03:23:54 +0000 Message-Id: <20200612032410.20864-6-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200612032410.20864-1-guinanx.sun@intel.com> References: <20200612032410.20864-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH 05/21] net/ixgbe/base: added API for NVM update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When Secure Boot is enabled access to the /dev/mem is forbidden for user-space applications and clients are reporting inability to use tools in Secure Boot Mode. The way to perform NVM update is to use ixgbe driver. Currently 10G Linux Base Driver has API which allows only EEPROM access. There is a need to extend IOCTL API to allow NVM and registers access. Signed-off-by: Piotr Skajewski Signed-off-by: Guinan Sun --- drivers/net/ixgbe/base/ixgbe_api.c | 13 ++++++++++ drivers/net/ixgbe/base/ixgbe_type.h | 40 +++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/net/ixgbe/base/ixgbe_api.c b/drivers/net/ixgbe/base/ixgbe_api.c index 9e4763a64..4d61513ec 100644 --- a/drivers/net/ixgbe/base/ixgbe_api.c +++ b/drivers/net/ixgbe/base/ixgbe_api.c @@ -95,6 +95,19 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) } hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; +#ifdef IXGBE_NVMUPD_SUPPORT + /* NVM Update features structure initialization */ + hw->nvmupd_features.major = IXGBE_NVMUPD_FEATURES_API_VER_MAJOR; + hw->nvmupd_features.minor = IXGBE_NVMUPD_FEATURES_API_VER_MINOR; + hw->nvmupd_features.size = sizeof(hw->nvmupd_features); + memset(hw->nvmupd_features.features, 0x0, + IXGBE_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN * + sizeof(*hw->nvmupd_features.features)); + + hw->nvmupd_features.features[0] = + IXGBE_NVMUPD_FEATURE_REGISTER_ACCESS_SUPPORT; +#endif /* IXGBE_NVMUPD_SUPPORT */ + return status; } diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h index 33ca659cd..c1ee4c680 100644 --- a/drivers/net/ixgbe/base/ixgbe_type.h +++ b/drivers/net/ixgbe/base/ixgbe_type.h @@ -169,6 +169,10 @@ #define IXGBE_FLA_X550EM_x IXGBE_FLA #define IXGBE_FLA_X550EM_a 0x15F68 #define IXGBE_FLA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FLA) +#define IXGBE_FLA_FL_SIZE_SHIFT_X540 17 +#define IXGBE_FLA_FL_SIZE_SHIFT_X550 12 +#define IXGBE_FLA_FL_SIZE_MASK_X540 (0x7 << IXGBE_FLA_FL_SIZE_SHIFT_X540) +#define IXGBE_FLA_FL_SIZE_MASK_X550 (0x7 << IXGBE_FLA_FL_SIZE_SHIFT_X550) #define IXGBE_EEMNGCTL 0x10110 #define IXGBE_EEMNGDATA 0x10114 @@ -1402,6 +1406,7 @@ struct ixgbe_dmac_config { #define IXGBE_BARCTRL_FLSIZE 0x0700 #define IXGBE_BARCTRL_FLSIZE_SHIFT 8 #define IXGBE_BARCTRL_CSRSIZE 0x2000 +#define IXGBE_BARCTRL_CSRSIZE_SHIFT 13 /* RSCCTL Bit Masks */ #define IXGBE_RSCCTL_RSCEN 0x01 @@ -3905,6 +3910,37 @@ struct ixgbe_hw_stats { u64 o2bspc; }; +#ifdef IXGBE_NVMUPD_SUPPORT +/* NVM Update commands */ +#define IXGBE_NVMUPD_CMD_REG_READ 0x0000000B +#define IXGBE_NVMUPD_CMD_REG_WRITE 0x0000000C + +/* NVM Update features API */ +#define IXGBE_NVMUPD_FEATURES_API_VER_MAJOR 0 +#define IXGBE_NVMUPD_FEATURES_API_VER_MINOR 0 +#define IXGBE_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12 +#define IXGBE_NVMUPD_EXEC_FEATURES 0xe +#define IXGBE_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0) +#define IXGBE_NVMUPD_FEATURE_REGISTER_ACCESS_SUPPORT BIT(1) + +#define IXGBE_NVMUPD_MOD_PNT_MASK 0xFF + +struct ixgbe_nvm_access { + u32 command; + u32 config; + u32 offset; /* in bytes */ + u32 data_size; /* in bytes */ + u8 data[1]; +}; + +struct ixgbe_nvm_features { + u8 major; + u8 minor; + u16 size; + u8 features[IXGBE_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN]; +}; + +#endif /* forward declaration */ struct ixgbe_hw; @@ -4200,6 +4236,10 @@ struct ixgbe_hw { bool allow_unsupported_sfp; bool wol_enabled; bool need_crosstalk_fix; +#ifdef IXGBE_NVMUPD_SUPPORT + /* NVM Update features */ + struct ixgbe_nvm_features nvmupd_features; +#endif }; #define ixgbe_call_func(hw, func, params, error) \