diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 9326401b4..7f7aa24e6 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -61,11 +61,11 @@ bnxt_ulp_flow_validate_args(const struct rte_flow_attr *attr,
 
 /* Function to create the rte flow. */
 static struct rte_flow *
-bnxt_ulp_flow_create(struct rte_eth_dev			*dev,
-		     const struct rte_flow_attr		*attr,
-		     const struct rte_flow_item		pattern[],
-		     const struct rte_flow_action	actions[],
-		     struct rte_flow_error		*error)
+bnxt_ulp_flow_create(struct rte_eth_dev *dev,
+		     const struct rte_flow_attr *attr,
+		     const struct rte_flow_item pattern[],
+		     const struct rte_flow_action actions[],
+		     struct rte_flow_error *error)
 {
 	struct bnxt_ulp_mapper_create_parms mapper_cparms = { 0 };
 	struct ulp_rte_parser_params params;
@@ -73,8 +73,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev			*dev,
 	uint32_t class_id, act_tmpl;
 	struct rte_flow *flow_id;
 	uint32_t fid;
-	uint8_t	*buffer;
-	uint32_t vnic;
 	int ret;
 
 	if (bnxt_ulp_flow_validate_args(attr,
@@ -97,14 +95,9 @@ bnxt_ulp_flow_create(struct rte_eth_dev			*dev,
 		params.dir = ULP_DIR_EGRESS;
 
 	/* copy the device port id and direction for further processing */
-	buffer = params.hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].spec;
-	rte_memcpy(buffer, &dev->data->port_id, sizeof(uint16_t));
-
-	/* Set the implicit vnic in the action property */
-	vnic = (uint32_t)bnxt_get_vnic_id(dev->data->port_id);
-	vnic = htonl(vnic);
-	rte_memcpy(&params.act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],
-		   &vnic, BNXT_ULP_ACT_PROP_SZ_VNIC);
+	ULP_UTIL_CHF_IDX_WR(&params, BNXT_ULP_CHF_IDX_INCOMING_IF,
+			    dev->data->port_id);
+	ULP_UTIL_CHF_IDX_WR(&params, BNXT_ULP_CHF_IDX_DIRECTION, params.dir);
 
 	/* Parse the rte flow pattern */
 	ret = bnxt_ulp_rte_parser_hdr_parse(pattern, &params);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index f70afa47f..a0aba403f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -357,7 +357,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
 	(void)tf_free_identifier(tfp, &free_parms);
 
 	BNXT_TF_DBG(ERR, "Ident process failed for %s:%s\n",
-		    ident->name,
+		    ident->description,
 		    (tbl->direction == TF_DIR_RX) ? "RX" : "TX");
 	return rc;
 }
@@ -405,7 +405,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
 			return -EINVAL;
 		}
 		break;
-	case BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP_SZ:
+	case BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ:
 		if (!ulp_operand_read(fld->result_operand,
 				      (uint8_t *)&idx, sizeof(uint16_t))) {
 			BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
index e04bfa094..e5f23ef27 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
@@ -6,40 +6,32 @@
 #include "ulp_matcher.h"
 #include "ulp_utils.h"
 
-/* Utility function to check if bitmap is zero */
-static inline
-int ulp_field_mask_is_zero(uint8_t *bitmap, uint32_t size)
+/* Utility function to calculate the class matcher hash */
+static uint32_t
+ulp_matcher_class_hash_calculate(uint64_t hi_sig, uint64_t lo_sig)
 {
-	while (size-- > 0) {
-		if (*bitmap != 0)
-			return 0;
-		bitmap++;
-	}
-	return 1;
-}
+	uint64_t hash;
 
-/* Utility function to check if bitmap is all ones */
-static inline int
-ulp_field_mask_is_ones(uint8_t *bitmap, uint32_t size)
-{
-	while (size-- > 0) {
-		if (*bitmap != 0xFF)
-			return 0;
-		bitmap++;
-	}
-	return 1;
+	hi_sig |= ((hi_sig % BNXT_ULP_CLASS_HID_HIGH_PRIME) <<
+		   BNXT_ULP_CLASS_HID_SHFTL);
+	lo_sig |= ((lo_sig % BNXT_ULP_CLASS_HID_LOW_PRIME) <<
+		   (BNXT_ULP_CLASS_HID_SHFTL + 2));
+	hash = hi_sig ^ lo_sig;
+	hash = (hash >> BNXT_ULP_CLASS_HID_SHFTR) & BNXT_ULP_CLASS_HID_MASK;
+	return (uint32_t)hash;
 }
 
-/* Utility function to check if bitmap is non zero */
-static inline int
-ulp_field_mask_notzero(uint8_t *bitmap, uint32_t size)
+/* Utility function to calculate the action matcher hash */
+static uint32_t
+ulp_matcher_action_hash_calculate(uint64_t hi_sig)
 {
-	while (size-- > 0) {
-		if (*bitmap != 0)
-			return 1;
-		bitmap++;
-	}
-	return 0;
+	uint64_t hash;
+
+	hi_sig |= ((hi_sig % BNXT_ULP_ACT_HID_HIGH_PRIME) <<
+		   BNXT_ULP_ACT_HID_SHFTL);
+	hash = hi_sig;
+	hash = (hash >> BNXT_ULP_ACT_HID_SHFTR) & BNXT_ULP_ACT_HID_MASK;
+	return (uint32_t)hash;
 }
 
 /* Utility function to mask the computed and internal proto headers. */
@@ -56,10 +48,6 @@ ulp_matcher_hdr_fields_normalize(struct ulp_rte_hdr_bitmap *hdr1,
 	ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_OI_VLAN);
 	ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_IO_VLAN);
 	ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_II_VLAN);
-	ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_O_L3);
-	ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_O_L4);
-	ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_I_L3);
-	ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_I_L4);
 }
 
 /*
@@ -70,82 +58,55 @@ int32_t
 ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
 			  uint32_t *class_id)
 {
-	struct bnxt_ulp_header_match_info	*sel_hdr_match;
-	uint32_t				hdr_num, idx, jdx;
-	uint32_t				match = 0;
-	struct ulp_rte_hdr_bitmap		hdr_bitmap_masked;
-	uint32_t				start_idx;
-	struct ulp_rte_hdr_field		*m_field;
-	struct bnxt_ulp_matcher_field_info	*sf;
-	struct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;
-	struct ulp_rte_act_bitmap *act_bitmap = &params->act_bitmap;
-	struct ulp_rte_hdr_field *hdr_field = params->hdr_field;
-
-	/* Select the ingress or egress template to match against */
-	if (params->dir == ULP_DIR_INGRESS) {
-		sel_hdr_match = ulp_ingress_hdr_match_list;
-		hdr_num = BNXT_ULP_INGRESS_HDR_MATCH_SZ;
+	struct ulp_rte_hdr_bitmap hdr_bitmap_masked;
+	struct bnxt_ulp_class_match_info *class_match;
+	uint32_t class_hid;
+	uint8_t vf_to_vf;
+	uint16_t tmpl_id;
+
+	/* Remove the hdr bit maps that are internal or computed */
+	ulp_matcher_hdr_fields_normalize(&params->hdr_bitmap,
+					 &hdr_bitmap_masked);
+
+	/* determine vf to vf flow */
+	if (params->dir == ULP_DIR_EGRESS &&
+	    ULP_BITMAP_ISSET(params->act_bitmap.bits,
+			     BNXT_ULP_ACTION_BIT_VNIC)) {
+		vf_to_vf = 1;
 	} else {
-		sel_hdr_match = ulp_egress_hdr_match_list;
-		hdr_num = BNXT_ULP_EGRESS_HDR_MATCH_SZ;
+		vf_to_vf = 0;
 	}
 
-	/* Remove the hdr bit maps that are internal or computed */
-	ulp_matcher_hdr_fields_normalize(hdr_bitmap, &hdr_bitmap_masked);
-
-	/* Loop through the list of class templates to find the match */
-	for (idx = 0; idx < hdr_num; idx++, sel_hdr_match++) {
-		if (ULP_BITSET_CMP(&sel_hdr_match->hdr_bitmap,
-				   &hdr_bitmap_masked)) {
-			/* no match found */
-			BNXT_TF_DBG(DEBUG, "Pattern Match failed template=%d\n",
-				    idx);
-			continue;
-		}
-		match = ULP_BITMAP_ISSET(act_bitmap->bits,
-					 BNXT_ULP_ACTION_BIT_VNIC);
-		if (match != sel_hdr_match->act_vnic) {
-			/* no match found */
-			BNXT_TF_DBG(DEBUG, "Vnic Match failed template=%d\n",
-				    idx);
-			continue;
-		} else {
-			match = 1;
-		}
-
-		/* Found a matching hdr bitmap, match the fields next */
-		start_idx = sel_hdr_match->start_idx;
-		for (jdx = 0; jdx < sel_hdr_match->num_entries; jdx++) {
-			m_field = &hdr_field[jdx + BNXT_ULP_HDR_FIELD_LAST - 1];
-			sf = &ulp_field_match[start_idx + jdx];
-			switch (sf->mask_opcode) {
-			case BNXT_ULP_FMF_MASK_ANY:
-				match &= ulp_field_mask_is_zero(m_field->mask,
-								m_field->size);
-				break;
-			case BNXT_ULP_FMF_MASK_EXACT:
-				match &= ulp_field_mask_is_ones(m_field->mask,
-								m_field->size);
-				break;
-			case BNXT_ULP_FMF_MASK_WILDCARD:
-				match &= ulp_field_mask_notzero(m_field->mask,
-								m_field->size);
-				break;
-			case BNXT_ULP_FMF_MASK_IGNORE:
-			default:
-				break;
-			}
-			if (!match)
-				break;
-		}
-		if (match) {
-			BNXT_TF_DBG(DEBUG,
-				    "Found matching pattern template %d\n",
-				    sel_hdr_match->class_tmpl_id);
-			*class_id = sel_hdr_match->class_tmpl_id;
-			return BNXT_TF_RC_SUCCESS;
-		}
+	/* calculate the hash of the given flow */
+	class_hid = ulp_matcher_class_hash_calculate(hdr_bitmap_masked.bits,
+						     params->fld_bitmap.bits);
+
+	/* validate the calculate hash values */
+	if (class_hid >= BNXT_ULP_CLASS_SIG_TBL_MAX_SZ)
+		goto error;
+	tmpl_id = ulp_class_sig_tbl[class_hid];
+	if (!tmpl_id)
+		goto error;
+
+	class_match = &ulp_class_match_list[tmpl_id];
+	if (ULP_BITMAP_CMP(&hdr_bitmap_masked, &class_match->hdr_sig)) {
+		BNXT_TF_DBG(DEBUG, "Proto Header does not match\n");
+		goto error;
+	}
+	if (ULP_BITMAP_CMP(&params->fld_bitmap, &class_match->field_sig)) {
+		BNXT_TF_DBG(DEBUG, "Field signature does not match\n");
+		goto error;
 	}
+	if (vf_to_vf != class_match->act_vnic) {
+		BNXT_TF_DBG(DEBUG, "Vnic Match failed\n");
+		goto error;
+	}
+	BNXT_TF_DBG(DEBUG, "Found matching pattern template %d\n",
+		    class_match->class_tid);
+	*class_id = class_match->class_tid;
+	return BNXT_TF_RC_SUCCESS;
+
+error:
 	BNXT_TF_DBG(DEBUG, "Did not find any matching template\n");
 	*class_id = 0;
 	return BNXT_TF_RC_ERROR;
@@ -159,29 +120,30 @@ int32_t
 ulp_matcher_action_match(struct ulp_rte_parser_params *params,
 			 uint32_t *act_id)
 {
-	struct bnxt_ulp_action_match_info	*sel_act_match;
-	uint32_t				act_num, idx;
-	struct ulp_rte_act_bitmap *act_bitmap = &params->act_bitmap;
-
-	/* Select the ingress or egress template to match against */
-	if (params->dir == ULP_DIR_INGRESS) {
-		sel_act_match = ulp_ingress_act_match_list;
-		act_num = BNXT_ULP_INGRESS_ACT_MATCH_SZ;
-	} else {
-		sel_act_match = ulp_egress_act_match_list;
-		act_num = BNXT_ULP_EGRESS_ACT_MATCH_SZ;
-	}
+	uint32_t act_hid;
+	uint16_t tmpl_id;
+	struct bnxt_ulp_act_match_info *act_match;
+
+	/* calculate the hash of the given flow action */
+	act_hid = ulp_matcher_action_hash_calculate(params->act_bitmap.bits);
 
-	/* Loop through the list of action templates to find the match */
-	for (idx = 0; idx < act_num; idx++, sel_act_match++) {
-		if (!ULP_BITSET_CMP(&sel_act_match->act_bitmap,
-				    act_bitmap)) {
-			*act_id = sel_act_match->act_tmpl_id;
-			BNXT_TF_DBG(DEBUG, "Found matching act template %u\n",
-				    *act_id);
-			return BNXT_TF_RC_SUCCESS;
-		}
+	/* validate the calculate hash values */
+	if (act_hid >= BNXT_ULP_ACT_SIG_TBL_MAX_SZ)
+		goto error;
+	tmpl_id = ulp_act_sig_tbl[act_hid];
+	if (!tmpl_id)
+		goto error;
+
+	act_match = &ulp_act_match_list[tmpl_id];
+	if (ULP_BITMAP_CMP(&params->act_bitmap, &act_match->act_sig)) {
+		BNXT_TF_DBG(DEBUG, "Action Header does not match\n");
+		goto error;
 	}
+	*act_id = act_match->act_tid;
+	BNXT_TF_DBG(DEBUG, "Found matching action template %u\n", *act_id);
+	return BNXT_TF_RC_SUCCESS;
+
+error:
 	BNXT_TF_DBG(DEBUG, "Did not find any matching action template\n");
 	*act_id = 0;
 	return BNXT_TF_RC_ERROR;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 2980e03b4..873f86494 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -11,25 +11,6 @@
 #include "ulp_utils.h"
 #include "tfp.h"
 
-/* Inline Func to read integer that is stored in big endian format */
-static inline void ulp_util_field_int_read(uint8_t *buffer,
-					   uint32_t *val)
-{
-	uint32_t temp_val;
-
-	memcpy(&temp_val, buffer, sizeof(uint32_t));
-	*val = rte_be_to_cpu_32(temp_val);
-}
-
-/* Inline Func to write integer that is stored in big endian format */
-static inline void ulp_util_field_int_write(uint8_t *buffer,
-					    uint32_t val)
-{
-	uint32_t temp_val = rte_cpu_to_be_32(val);
-
-	memcpy(buffer, &temp_val, sizeof(uint32_t));
-}
-
 /* Utility function to skip the void items. */
 static inline int32_t
 ulp_rte_item_skip_void(const struct rte_flow_item **item, uint32_t increment)
@@ -45,6 +26,25 @@ ulp_rte_item_skip_void(const struct rte_flow_item **item, uint32_t increment)
 	return 0;
 }
 
+/* Utility function to update the field_bitmap */
+static void
+ulp_rte_parser_field_bitmap_update(struct ulp_rte_parser_params *params,
+				   uint32_t idx)
+{
+	struct ulp_rte_hdr_field *field;
+
+	field = &params->hdr_field[idx];
+	if (ulp_bitmap_notzero(field->mask, field->size)) {
+		ULP_INDEX_BITMAP_SET(params->fld_bitmap.bits, idx);
+		/* Not exact match */
+		if (!ulp_bitmap_is_ones(field->mask, field->size))
+			ULP_BITMAP_SET(params->fld_bitmap.bits,
+				       BNXT_ULP_MATCH_TYPE_BITMASK_WM);
+	} else {
+		ULP_INDEX_BITMAP_RESET(params->fld_bitmap.bits, idx);
+	}
+}
+
 /* Utility function to copy field spec items */
 static struct ulp_rte_hdr_field *
 ulp_rte_parser_fld_copy(struct ulp_rte_hdr_field *field,
@@ -64,9 +64,10 @@ ulp_rte_prsr_mask_copy(struct ulp_rte_parser_params *params,
 		       const void *buffer,
 		       uint32_t size)
 {
-	struct ulp_rte_hdr_field	*field = &params->hdr_field[*idx];
+	struct ulp_rte_hdr_field *field = &params->hdr_field[*idx];
 
 	memcpy(field->mask, buffer, size);
+	ulp_rte_parser_field_bitmap_update(params, *idx);
 	*idx = *idx + 1;
 }
 
@@ -81,7 +82,11 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
 	const struct rte_flow_item *item = pattern;
 	struct bnxt_ulp_rte_hdr_info *hdr_info;
 
-	params->field_idx = BNXT_ULP_HDR_FIELD_LAST;
+	params->field_idx = BNXT_ULP_PROTO_HDR_SVIF_NUM;
+	if (params->dir == ULP_DIR_EGRESS)
+		ULP_BITMAP_SET(params->hdr_bitmap.bits,
+			       BNXT_ULP_FLOW_DIR_BITMASK_EGR);
+
 	/* Parse all the items in the pattern */
 	while (item && item->type != RTE_FLOW_ITEM_TYPE_END) {
 		/* get the header information from the flow_hdr_info table */
@@ -141,6 +146,8 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
 		}
 		action_item++;
 	}
+	/* update the implied VNIC */
+	ulp_rte_parser_vnic_process(params);
 	return BNXT_TF_RC_SUCCESS;
 }
 
@@ -153,69 +160,78 @@ ulp_rte_parser_svif_set(struct ulp_rte_parser_params *params,
 {
 	uint16_t port_id = svif;
 	uint32_t dir = 0;
+	struct ulp_rte_hdr_field *hdr_field;
 
 	if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF)) {
 		BNXT_TF_DBG(ERR,
-			    "SVIF already set,"
-			    " multiple sources not supported\n");
+			    "SVIF already set,multiple source not support'd\n");
 		return BNXT_TF_RC_ERROR;
 	}
 
-	/* Update the hdr_bitmap with BNXT_ULP_HDR_PROTO_SVIF. */
+	/*update the hdr_bitmap with BNXT_ULP_HDR_PROTO_SVIF */
 	ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF);
 
 	if (proto == RTE_FLOW_ITEM_TYPE_PORT_ID) {
-		/* perform the conversion from dpdk port to svif */
-		dir = params->dir;
+		dir = ULP_UTIL_CHF_IDX_RD(params,
+					  BNXT_ULP_CHF_IDX_DIRECTION);
+		/* perform the conversion from dpdk port to bnxt svif */
 		if (dir == ULP_DIR_EGRESS)
 			svif = bnxt_get_svif(port_id, true);
 		else
 			svif = bnxt_get_svif(port_id, false);
 	}
-
-	memcpy(params->hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].spec,
-	       &svif, sizeof(svif));
-	memcpy(params->hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].mask,
-	       &mask, sizeof(mask));
-	params->hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].size = sizeof(svif);
+	hdr_field = &params->hdr_field[BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX];
+	memcpy(hdr_field->spec, &svif, sizeof(svif));
+	memcpy(hdr_field->mask, &mask, sizeof(mask));
+	hdr_field->size = sizeof(svif);
 	return BNXT_TF_RC_SUCCESS;
 }
 
-/* Function to handle the parsing of the RTE port id
- */
+/* Function to handle the parsing of the RTE port id */
 int32_t
 ulp_rte_parser_svif_process(struct ulp_rte_parser_params *params)
 {
 	uint16_t port_id = 0;
-	uint8_t	*buffer;
 	uint16_t svif_mask = 0xFFFF;
 
 	if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF))
 		return BNXT_TF_RC_SUCCESS;
 
-	/* SVIF not set. So get the port id and direction */
-	buffer = params->hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].spec;
-	memcpy(&port_id, buffer, sizeof(port_id));
-	memset(buffer, 0, RTE_PARSER_FLOW_HDR_FIELD_SIZE);
+	/* SVIF not set. So get the port id */
+	port_id = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_INCOMING_IF);
 
-	return ulp_rte_parser_svif_set(params,
-				       RTE_FLOW_ITEM_TYPE_PORT_ID,
+	/* Update the SVIF details */
+	return ulp_rte_parser_svif_set(params, RTE_FLOW_ITEM_TYPE_PORT_ID,
 				       port_id, svif_mask);
 }
 
+/* Function to handle the implicit VNIC RTE port id */
+int32_t
+ulp_rte_parser_vnic_process(struct ulp_rte_parser_params *params)
+{
+	struct ulp_rte_act_bitmap *act = &params->act_bitmap;
+
+	if (ULP_BITMAP_ISSET(act->bits, BNXT_ULP_ACTION_BIT_VNIC) ||
+	    ULP_BITMAP_ISSET(act->bits, BNXT_ULP_ACTION_BIT_VPORT))
+		return BNXT_TF_RC_SUCCESS;
+
+	/* Update the vnic details */
+	ulp_rte_pf_act_handler(NULL, params);
+	return BNXT_TF_RC_SUCCESS;
+}
+
 /* Function to handle the parsing of RTE Flow item PF Header. */
 int32_t
 ulp_rte_pf_hdr_handler(const struct rte_flow_item *item,
 		       struct ulp_rte_parser_params *params)
 {
 	uint16_t port_id = 0;
-	uint8_t	*buffer;
 	uint16_t svif_mask = 0xFFFF;
 
-	buffer = params->hdr_field[BNXT_ULP_HDR_FIELD_SVIF_INDEX].spec;
-	memcpy(&port_id, buffer, sizeof(port_id));
-	memset(buffer, 0, RTE_PARSER_FLOW_HDR_FIELD_SIZE);
+	/* Get the port id */
+	port_id = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_INCOMING_IF);
 
+	/* Update the SVIF details */
 	return ulp_rte_parser_svif_set(params,
 				       item->type,
 				       port_id, svif_mask);
@@ -345,15 +361,11 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
 	const struct rte_flow_item_vlan *vlan_spec = item->spec;
 	const struct rte_flow_item_vlan *vlan_mask = item->mask;
 	struct ulp_rte_hdr_field *field;
-	struct ulp_rte_hdr_bitmap *hdr_bitmap;
+	struct ulp_rte_hdr_bitmap	*hdr_bit;
 	uint32_t idx = params->vlan_idx;
 	uint16_t vlan_tag, priority;
-	uint32_t outer_vtag_num = 0, inner_vtag_num = 0;
-	uint8_t *outer_tag_buff;
-	uint8_t *inner_tag_buff;
-
-	outer_tag_buff = params->hdr_field[BNXT_ULP_HDR_FIELD_O_VTAG_NUM].spec;
-	inner_tag_buff = params->hdr_field[BNXT_ULP_HDR_FIELD_I_VTAG_NUM].spec;
+	uint32_t outer_vtag_num;
+	uint32_t inner_vtag_num;
 
 	/*
 	 * Copy the rte_flow_item for vlan into hdr_field using Vlan
@@ -393,64 +405,53 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
 	params->vlan_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM;
 
 	/* Get the outer tag and inner tag counts */
-	ulp_util_field_int_read(outer_tag_buff, &outer_vtag_num);
-	ulp_util_field_int_read(inner_tag_buff, &inner_vtag_num);
+	outer_vtag_num = ULP_UTIL_CHF_IDX_RD(params,
+					     BNXT_ULP_CHF_IDX_O_VTAG_NUM);
+	inner_vtag_num = ULP_UTIL_CHF_IDX_RD(params,
+					     BNXT_ULP_CHF_IDX_I_VTAG_NUM);
 
 	/* Update the hdr_bitmap of the vlans */
-	hdr_bitmap  = &params->hdr_bitmap;
-	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
-	    !ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_OO_VLAN)) {
+	hdr_bit = &params->hdr_bitmap;
+	if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
+	    !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN)) {
 		/* Set the outer vlan bit and update the vlan tag num */
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_OO_VLAN);
+		ULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN);
 		outer_vtag_num++;
-		ulp_util_field_int_write(outer_tag_buff, outer_vtag_num);
-		params->hdr_field[BNXT_ULP_HDR_FIELD_O_VTAG_NUM].size =
-							sizeof(uint32_t);
-	} else if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
-		   ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				    BNXT_ULP_HDR_BIT_OO_VLAN) &&
-		   !ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				     BNXT_ULP_HDR_BIT_OI_VLAN)) {
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_NUM,
+				    outer_vtag_num);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_PRESENT, 1);
+	} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
+		   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN) &&
+		   !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN)) {
 		/* Set the outer vlan bit and update the vlan tag num */
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_OI_VLAN);
+		ULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN);
 		outer_vtag_num++;
-		ulp_util_field_int_write(outer_tag_buff, outer_vtag_num);
-		params->hdr_field[BNXT_ULP_HDR_FIELD_O_VTAG_NUM].size =
-							    sizeof(uint32_t);
-	} else if (ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				    BNXT_ULP_HDR_BIT_O_ETH) &&
-		   ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				    BNXT_ULP_HDR_BIT_OO_VLAN) &&
-		   ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				    BNXT_ULP_HDR_BIT_OI_VLAN) &&
-		   ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				    BNXT_ULP_HDR_BIT_I_ETH) &&
-		   !ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				     BNXT_ULP_HDR_BIT_IO_VLAN)) {
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_NUM,
+				    outer_vtag_num);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_TWO_VTAGS, 1);
+	} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
+		   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN) &&
+		   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN) &&
+		   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
+		   !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_IO_VLAN)) {
 		/* Set the inner vlan bit and update the vlan tag num */
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_IO_VLAN);
+		ULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_IO_VLAN);
 		inner_vtag_num++;
-		ulp_util_field_int_write(inner_tag_buff, inner_vtag_num);
-		params->hdr_field[BNXT_ULP_HDR_FIELD_I_VTAG_NUM].size =
-							    sizeof(uint32_t);
-	} else if (ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				    BNXT_ULP_HDR_BIT_O_ETH) &&
-		   ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				    BNXT_ULP_HDR_BIT_OO_VLAN) &&
-		   ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				    BNXT_ULP_HDR_BIT_OI_VLAN) &&
-		   ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				    BNXT_ULP_HDR_BIT_I_ETH) &&
-		   ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				    BNXT_ULP_HDR_BIT_IO_VLAN) &&
-		   !ULP_BITMAP_ISSET(hdr_bitmap->bits,
-				     BNXT_ULP_HDR_BIT_II_VLAN)) {
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_NUM,
+				    inner_vtag_num);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_PRESENT, 1);
+	} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
+		   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN) &&
+		   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN) &&
+		   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
+		   ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_IO_VLAN) &&
+		   !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_II_VLAN)) {
 		/* Set the inner vlan bit and update the vlan tag num */
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_II_VLAN);
+		ULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_II_VLAN);
 		inner_vtag_num++;
-		ulp_util_field_int_write(inner_tag_buff, inner_vtag_num);
-		params->hdr_field[BNXT_ULP_HDR_FIELD_I_VTAG_NUM].size =
-							    sizeof(uint32_t);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_NUM,
+				    inner_vtag_num);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_TWO_VTAGS, 1);
 	} else {
 		BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n");
 		return BNXT_TF_RC_ERROR;
@@ -469,8 +470,10 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
 	struct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;
 	uint32_t idx = params->field_idx;
 	uint32_t size;
+	uint32_t inner_l3, outer_l3;
 
-	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L3)) {
+	inner_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L3);
+	if (inner_l3) {
 		BNXT_TF_DBG(ERR, "Parse Error:Third L3 header not supported\n");
 		return BNXT_TF_RC_ERROR;
 	}
@@ -557,14 +560,17 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
 	params->field_idx += BNXT_ULP_PROTO_HDR_IPV4_NUM;
 
 	/* Set the ipv4 header bitmap and computed l3 header bitmaps */
-	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L3) ||
+	outer_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L3);
+	if (outer_l3 ||
 	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) ||
 	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) {
 		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4);
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L3);
+		inner_l3++;
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L3, inner_l3);
 	} else {
 		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4);
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L3);
+		outer_l3++;
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L3, outer_l3);
 	}
 	return BNXT_TF_RC_SUCCESS;
 }
@@ -580,8 +586,10 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
 	struct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;
 	uint32_t idx = params->field_idx;
 	uint32_t size;
+	uint32_t inner_l3, outer_l3;
 
-	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L3)) {
+	inner_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L3);
+	if (inner_l3) {
 		BNXT_TF_DBG(ERR, "Parse Error: 3'rd L3 header not supported\n");
 		return BNXT_TF_RC_ERROR;
 	}
@@ -640,14 +648,15 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
 	params->field_idx += BNXT_ULP_PROTO_HDR_IPV6_NUM;
 
 	/* Set the ipv6 header bitmap and computed l3 header bitmaps */
-	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L3) ||
+	outer_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L3);
+	if (outer_l3 ||
 	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) ||
 	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) {
 		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6);
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L3);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L3, 1);
 	} else {
 		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6);
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L3);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L3, 1);
 	}
 	return BNXT_TF_RC_SUCCESS;
 }
@@ -663,8 +672,10 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
 	struct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;
 	uint32_t idx = params->field_idx;
 	uint32_t size;
+	uint32_t inner_l4, outer_l4;
 
-	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L4)) {
+	inner_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L4);
+	if (inner_l4) {
 		BNXT_TF_DBG(ERR, "Parse Err:Third L4 header not supported\n");
 		return BNXT_TF_RC_ERROR;
 	}
@@ -710,14 +721,15 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
 	params->field_idx += BNXT_ULP_PROTO_HDR_UDP_NUM;
 
 	/* Set the udp header bitmap and computed l4 header bitmaps */
-	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L4) ||
+	outer_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L4);
+	if (outer_l4 ||
 	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
 	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
 		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP);
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L4);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L4, 1);
 	} else {
 		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP);
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L4);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L4, 1);
 	}
 	return BNXT_TF_RC_SUCCESS;
 }
@@ -733,8 +745,10 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
 	struct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;
 	uint32_t idx = params->field_idx;
 	uint32_t size;
+	uint32_t inner_l4, outer_l4;
 
-	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L4)) {
+	inner_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L4);
+	if (inner_l4) {
 		BNXT_TF_DBG(ERR, "Parse Error:Third L4 header not supported\n");
 		return BNXT_TF_RC_ERROR;
 	}
@@ -817,14 +831,15 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
 	params->field_idx += BNXT_ULP_PROTO_HDR_TCP_NUM;
 
 	/* Set the udp header bitmap and computed l4 header bitmaps */
-	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L4) ||
+	outer_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L4);
+	if (outer_l4 ||
 	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
 	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
 		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP);
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_L4);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L4, 1);
 	} else {
 		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP);
-		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_L4);
+		ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L4, 1);
 	}
 	return BNXT_TF_RC_SUCCESS;
 }
@@ -1181,22 +1196,19 @@ ulp_rte_count_act_handler(const struct rte_flow_action *action_item,
 /* Function to handle the parsing of RTE Flow action PF. */
 int32_t
 ulp_rte_pf_act_handler(const struct rte_flow_action *action_item __rte_unused,
-		       struct ulp_rte_parser_params *param)
+		       struct ulp_rte_parser_params *params)
 {
-	uint8_t *svif_buf;
-	uint8_t *vnic_buffer;
 	uint32_t svif;
 
 	/* Update the hdr_bitmap with vnic bit */
-	ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACTION_BIT_VNIC);
+	ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_VNIC);
 
 	/* copy the PF of the current device into VNIC Property */
-	svif_buf = &param->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC];
-	ulp_util_field_int_read(svif_buf, &svif);
-	svif = (uint32_t)bnxt_get_vnic_id(svif);
-	svif = htonl(svif);
-	vnic_buffer = &param->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC];
-	ulp_util_field_int_write(vnic_buffer, svif);
+	svif = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_INCOMING_IF);
+	svif = bnxt_get_vnic_id(svif);
+	svif = rte_cpu_to_be_32(svif);
+	memcpy(&params->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],
+	       &svif, BNXT_ULP_ACT_PROP_SZ_VNIC);
 
 	return BNXT_TF_RC_SUCCESS;
 }
@@ -1207,6 +1219,7 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item,
 		       struct ulp_rte_parser_params *param)
 {
 	const struct rte_flow_action_vf *vf_action;
+	uint32_t pid;
 
 	vf_action = action_item->conf;
 	if (vf_action) {
@@ -1216,9 +1229,10 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item,
 			return BNXT_TF_RC_PARSE_ERR;
 		}
 		/* TBD: Update the computed VNIC using VF conversion */
+		pid = bnxt_get_vnic_id(vf_action->id);
+		pid = rte_cpu_to_be_32(pid);
 		memcpy(&param->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],
-		       &vf_action->id,
-		       BNXT_ULP_ACT_PROP_SZ_VNIC);
+		       &pid, BNXT_ULP_ACT_PROP_SZ_VNIC);
 	}
 
 	/* Update the hdr_bitmap with count */
@@ -1232,6 +1246,7 @@ ulp_rte_port_id_act_handler(const struct rte_flow_action *act_item,
 			    struct ulp_rte_parser_params *param)
 {
 	const struct rte_flow_action_port_id *port_id;
+	uint32_t pid;
 
 	port_id = act_item->conf;
 	if (port_id) {
@@ -1241,9 +1256,10 @@ ulp_rte_port_id_act_handler(const struct rte_flow_action *act_item,
 			return BNXT_TF_RC_PARSE_ERR;
 		}
 		/* TBD: Update the computed VNIC using port conversion */
+		pid = bnxt_get_vnic_id(port_id->id);
+		pid = rte_cpu_to_be_32(pid);
 		memcpy(&param->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],
-		       &port_id->id,
-		       BNXT_ULP_ACT_PROP_SZ_VNIC);
+		       &pid, BNXT_ULP_ACT_PROP_SZ_VNIC);
 	}
 
 	/* Update the hdr_bitmap with count */
@@ -1257,6 +1273,7 @@ ulp_rte_phy_port_act_handler(const struct rte_flow_action *action_item,
 			     struct ulp_rte_parser_params *prm)
 {
 	const struct rte_flow_action_phy_port *phy_port;
+	uint32_t pid;
 
 	phy_port = action_item->conf;
 	if (phy_port) {
@@ -1265,9 +1282,10 @@ ulp_rte_phy_port_act_handler(const struct rte_flow_action *action_item,
 				    "Parse Err:Port Original not supported\n");
 			return BNXT_TF_RC_PARSE_ERR;
 		}
+		pid = bnxt_get_vnic_id(phy_port->index);
+		pid = rte_cpu_to_be_32(pid);
 		memcpy(&prm->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VPORT],
-		       &phy_port->index,
-		       BNXT_ULP_ACT_PROP_SZ_VPORT);
+		       &pid, BNXT_ULP_ACT_PROP_SZ_VPORT);
 	}
 
 	/* Update the hdr_bitmap with count */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 4cc9dcc4e..cbc8a43de 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -24,6 +24,10 @@
 int32_t
 ulp_rte_parser_svif_process(struct ulp_rte_parser_params *params);
 
+/* Function to handle the implicit VNIC RTE port id */
+int32_t
+ulp_rte_parser_vnic_process(struct ulp_rte_parser_params *params);
+
 /*
  * Function to handle the parsing of RTE Flows and placing
  * the RTE flow items into the ulp structures.
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index 411f1e3df..25a558a4e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2019 Broadcom
+ * Copyright(c) 2014-2020 Broadcom
  * All rights reserved.
  */
 
@@ -30,6 +30,8 @@ uint32_t ulp_act_prop_map_table[] = {
 		BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM,
 	[BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM] =
 		BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM,
+	[BNXT_ULP_ACT_PROP_IDX_PORT_ID] =
+		BNXT_ULP_ACT_PROP_SZ_PORT_ID,
 	[BNXT_ULP_ACT_PROP_IDX_VNIC] =
 		BNXT_ULP_ACT_PROP_SZ_VNIC,
 	[BNXT_ULP_ACT_PROP_IDX_VPORT] =
@@ -505,8 +507,55 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
 	}
 };
 
+uint32_t bnxt_ulp_encap_vtag_map[] = {
+	[0] = BNXT_ULP_ENCAP_VTAG_ENCODING_NOP,
+	[1] = BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_ECAP_PRI,
+	[2] = BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_ECAP_PRI
+};
+
+uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
+	[BNXT_ULP_CLASS_HID_0092] = 1
+};
+
+struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
+	[1] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0092,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 0,
+	.act_vnic = 0,
+	.wc_pri = 0
+	}
+};
+
+uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
+	[BNXT_ULP_ACT_HID_0029] = 1
+};
+
+struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
+	[1] = {
+	.act_hid = BNXT_ULP_ACT_HID_0029,
+	.act_sig = { .bits =
+		BNXT_ULP_ACTION_BIT_MARK |
+		BNXT_ULP_ACTION_BIT_RSS |
+		BNXT_ULP_ACTION_BIT_VNIC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 0
+	}
+};
+
 struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
-	[((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) | BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+	[((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 3,
 	.start_tbl_idx = 0
@@ -528,7 +577,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.ident_start_idx = 0,
-	.ident_nums = 1,
+	.ident_nums = 2,
 	.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
 	.critical_resource = 0,
 	.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
@@ -546,7 +595,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
 	.result_start_idx = 13,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
-	.ident_start_idx = 1,
+	.ident_start_idx = 2,
 	.ident_nums = 1,
 	.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
 	.critical_resource = 0,
@@ -560,12 +609,11 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.key_start_idx = 55,
 	.blob_key_bit_size = 448,
-	.key_bit_size = 197,
+	.key_bit_size = 448,
 	.key_num_fields = 11,
 	.result_start_idx = 21,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
-	.ident_start_idx = 2,
 	.ident_nums = 0,
 	.mark_enable = BNXT_ULP_MARK_ENABLE_YES,
 	.critical_resource = 1,
@@ -595,24 +643,22 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {(BNXT_ULP_HF0_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF0_O_ETH_DMAC & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
-	.mask_operand = {(BNXT_ULP_HF0_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF0_SVIF_INDEX & 0xff,
+	.mask_operand = {(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {(BNXT_ULP_HF0_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF0_SVIF_INDEX & 0xff,
+	.spec_operand = {(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -859,8 +905,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
-	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_operand = {BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -895,8 +942,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
-	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_operand = {BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -949,14 +997,15 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
-	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_operand = {BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
 	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
 	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -967,7 +1016,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
-	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -1003,8 +1052,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
-	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_operand = {BNXT_ULP_SYM_TL2_HDR_TYPE_DIX,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -1012,7 +1062,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
-	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -1038,9 +1088,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
-	.spec_operand = {0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+	.spec_operand = {(BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -1103,8 +1155,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {(BNXT_ULP_HF0_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF0_O_UDP_DST_PORT & 0xff,
+	.spec_operand = {(BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF0_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -1114,8 +1166,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {(BNXT_ULP_HF0_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF0_O_UDP_SRC_PORT & 0xff,
+	.spec_operand = {(BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -1135,8 +1187,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {(BNXT_ULP_HF0_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF0_O_IPV4_DST_ADDR & 0xff,
+	.spec_operand = {(BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -1146,8 +1198,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {(BNXT_ULP_HF0_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF0_O_IPV4_SRC_ADDR & 0xff,
+	.spec_operand = {(BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -1156,11 +1208,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {(BNXT_ULP_HF0_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF0_O_ETH_SMAC & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 24,
@@ -1187,124 +1237,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
-	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-	}
-};
-
-struct bnxt_ulp_header_match_info ulp_ingress_hdr_match_list[] = {
-	{
-	.hdr_bitmap = { .bits =
-		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP },
-	.start_idx = 0,
-	.num_entries = 24,
-	.class_tmpl_id = 0,
-	.act_vnic = 0
-	}
-};
-
-struct bnxt_ulp_header_match_info ulp_egress_hdr_match_list[] = {
-};
-
-struct bnxt_ulp_matcher_field_info ulp_field_match[] = {
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_ANY,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_ANY,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
-	},
-	{
-	.mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
-	.spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+	.spec_operand = {(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	}
 };
 
@@ -1319,9 +1256,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 7,
-	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+	.result_operand = {(BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -1410,8 +1349,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 10,
 	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
-	.result_operand = {(0x00fd >> 8) & 0xff,
-		0x00fd & 0xff,
+	.result_operand = {(0x00f9 >> 8) & 0xff,
+		0x00f9 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -1423,9 +1362,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	},
 	{
 	.field_bit_size = 8,
-	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+	.result_operand = {(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -1462,7 +1403,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -1500,6 +1441,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 };
 
 struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_PROF_FUNC,
+	.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0,
+	.ident_bit_size = 7,
+	.ident_bit_pos = 47
+	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
 	.ident_type = TF_IDENT_TYPE_L2_CTXT,
@@ -1516,20 +1464,9 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {
 	}
 };
 
-struct bnxt_ulp_action_match_info ulp_ingress_act_match_list[] = {
-	{
-	.act_bitmap = { .bits =
-		BNXT_ULP_ACTION_BIT_MARK |
-		BNXT_ULP_ACTION_BIT_RSS },
-	.act_tmpl_id = 0
-	}
-};
-
-struct bnxt_ulp_action_match_info ulp_egress_act_match_list[] = {
-};
-
 struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {
-	[((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) | BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+	[((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 1,
 	.start_tbl_idx = 0
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index dfab266d6..94d425315 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2019 Broadcom
+ * Copyright(c) 2014-2020 Broadcom
  * All rights reserved.
  */
 
@@ -11,12 +11,23 @@
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_
 
+#define BNXT_ULP_REGFILE_MAX_SZ 15
 #define BNXT_ULP_MAX_NUM_DEVICES 4
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_INGRESS_HDR_MATCH_SZ 2
-#define BNXT_ULP_EGRESS_HDR_MATCH_SZ 1
-#define BNXT_ULP_INGRESS_ACT_MATCH_SZ 2
-#define BNXT_ULP_EGRESS_ACT_MATCH_SZ 1
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 2
+#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919
+#define BNXT_ULP_CLASS_HID_SHFTR 0
+#define BNXT_ULP_CLASS_HID_SHFTL 23
+#define BNXT_ULP_CLASS_HID_MASK 255
+#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 2
+#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
+#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
+#define BNXT_ULP_ACT_HID_SHFTR 0
+#define BNXT_ULP_ACT_HID_SHFTL 23
+#define BNXT_ULP_ACT_HID_MASK 255
 
 enum bnxt_ulp_action_bit {
 	BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
@@ -54,24 +65,20 @@ enum bnxt_ulp_hdr_bit {
 	BNXT_ULP_HDR_BIT_O_ETH               = 0x0000000000000002,
 	BNXT_ULP_HDR_BIT_OO_VLAN             = 0x0000000000000004,
 	BNXT_ULP_HDR_BIT_OI_VLAN             = 0x0000000000000008,
-	BNXT_ULP_HDR_BIT_O_L3                = 0x0000000000000010,
-	BNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000020,
-	BNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000040,
-	BNXT_ULP_HDR_BIT_O_L4                = 0x0000000000000080,
-	BNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000100,
-	BNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000200,
-	BNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000400,
-	BNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000800,
-	BNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000001000,
-	BNXT_ULP_HDR_BIT_IO_VLAN             = 0x0000000000002000,
-	BNXT_ULP_HDR_BIT_II_VLAN             = 0x0000000000004000,
-	BNXT_ULP_HDR_BIT_I_L3                = 0x0000000000008000,
-	BNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000010000,
-	BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000020000,
-	BNXT_ULP_HDR_BIT_I_L4                = 0x0000000000040000,
-	BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000080000,
-	BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000100000,
-	BNXT_ULP_HDR_BIT_LAST                = 0x0000000000200000
+	BNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000010,
+	BNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000020,
+	BNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000040,
+	BNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000080,
+	BNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000100,
+	BNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000200,
+	BNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000000400,
+	BNXT_ULP_HDR_BIT_IO_VLAN             = 0x0000000000000800,
+	BNXT_ULP_HDR_BIT_II_VLAN             = 0x0000000000001000,
+	BNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000002000,
+	BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000004000,
+	BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000008000,
+	BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000010000,
+	BNXT_ULP_HDR_BIT_LAST                = 0x0000000000020000
 };
 
 enum bnxt_ulp_act_type {
@@ -82,30 +89,42 @@ enum bnxt_ulp_act_type {
 };
 
 enum bnxt_ulp_byte_order {
-	BNXT_ULP_BYTE_ORDER_BE,
-	BNXT_ULP_BYTE_ORDER_LE,
-	BNXT_ULP_BYTE_ORDER_LAST
+	BNXT_ULP_BYTE_ORDER_BE = 0,
+	BNXT_ULP_BYTE_ORDER_LE = 1,
+	BNXT_ULP_BYTE_ORDER_LAST = 2
 };
 
-enum bnxt_ulp_device_id {
-	BNXT_ULP_DEVICE_ID_WH_PLUS,
-	BNXT_ULP_DEVICE_ID_THOR,
-	BNXT_ULP_DEVICE_ID_STINGRAY,
-	BNXT_ULP_DEVICE_ID_STINGRAY2,
-	BNXT_ULP_DEVICE_ID_LAST
+enum bnxt_ulp_chf_idx {
+	BNXT_ULP_CHF_IDX_MPLS_TAG_NUM = 0,
+	BNXT_ULP_CHF_IDX_O_VTAG_NUM = 1,
+	BNXT_ULP_CHF_IDX_O_VTAG_PRESENT = 2,
+	BNXT_ULP_CHF_IDX_O_TWO_VTAGS = 3,
+	BNXT_ULP_CHF_IDX_I_VTAG_NUM = 4,
+	BNXT_ULP_CHF_IDX_I_VTAG_PRESENT = 5,
+	BNXT_ULP_CHF_IDX_I_TWO_VTAGS = 6,
+	BNXT_ULP_CHF_IDX_INCOMING_IF = 7,
+	BNXT_ULP_CHF_IDX_DIRECTION = 8,
+	BNXT_ULP_CHF_IDX_SVIF = 9,
+	BNXT_ULP_CHF_IDX_O_L3 = 10,
+	BNXT_ULP_CHF_IDX_I_L3 = 11,
+	BNXT_ULP_CHF_IDX_O_L4 = 12,
+	BNXT_ULP_CHF_IDX_I_L4 = 13,
+	BNXT_ULP_CHF_IDX_LAST = 14
 };
 
-enum bnxt_ulp_fmf_mask {
-	BNXT_ULP_FMF_MASK_IGNORE,
-	BNXT_ULP_FMF_MASK_ANY,
-	BNXT_ULP_FMF_MASK_EXACT,
-	BNXT_ULP_FMF_MASK_WILDCARD,
-	BNXT_ULP_FMF_MASK_LAST
+enum bnxt_ulp_device_id {
+	BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
+	BNXT_ULP_DEVICE_ID_THOR = 1,
+	BNXT_ULP_DEVICE_ID_STINGRAY = 2,
+	BNXT_ULP_DEVICE_ID_STINGRAY2 = 3,
+	BNXT_ULP_DEVICE_ID_LAST = 4
 };
 
-enum bnxt_ulp_fmf_spec {
-	BNXT_ULP_FMF_SPEC_IGNORE = 0,
-	BNXT_ULP_FMF_SPEC_LAST = 1
+enum bnxt_ulp_hdr_type {
+	BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
+	BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
+	BNXT_ULP_HDR_TYPE_END = 2,
+	BNXT_ULP_HDR_TYPE_LAST = 3
 };
 
 enum bnxt_ulp_mark_enable {
@@ -114,21 +133,6 @@ enum bnxt_ulp_mark_enable {
 	BNXT_ULP_MARK_ENABLE_LAST = 2
 };
 
-enum bnxt_ulp_hdr_field {
-	BNXT_ULP_HDR_FIELD_MPLS_TAG_NUM = 0,
-	BNXT_ULP_HDR_FIELD_O_VTAG_NUM = 1,
-	BNXT_ULP_HDR_FIELD_I_VTAG_NUM = 2,
-	BNXT_ULP_HDR_FIELD_SVIF_INDEX = 3,
-	BNXT_ULP_HDR_FIELD_LAST = 4
-};
-
-enum bnxt_ulp_hdr_type {
-	BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
-	BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
-	BNXT_ULP_HDR_TYPE_END = 2,
-	BNXT_ULP_HDR_TYPE_LAST = 3
-};
-
 enum bnxt_ulp_mask_opc {
 	BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
 	BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
@@ -137,6 +141,12 @@ enum bnxt_ulp_mask_opc {
 	BNXT_ULP_MASK_OPC_LAST = 4
 };
 
+enum bnxt_ulp_match_type {
+	BNXT_ULP_MATCH_TYPE_EM = 0,
+	BNXT_ULP_MATCH_TYPE_WC = 1,
+	BNXT_ULP_MATCH_TYPE_LAST = 2
+};
+
 enum bnxt_ulp_priority {
 	BNXT_ULP_PRIORITY_LEVEL_0 = 0,
 	BNXT_ULP_PRIORITY_LEVEL_1 = 1,
@@ -151,20 +161,22 @@ enum bnxt_ulp_priority {
 };
 
 enum bnxt_ulp_regfile_index {
-	BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 0,
-	BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 1,
-	BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 2,
-	BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 3,
-	BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 4,
-	BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 5,
-	BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 6,
-	BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 7,
-	BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN = 8,
-	BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 9,
-	BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 10,
-	BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 11,
-	BNXT_ULP_REGFILE_INDEX_NOT_USED = 12,
-	BNXT_ULP_REGFILE_INDEX_LAST = 13
+	BNXT_ULP_REGFILE_INDEX_CLASS_TID = 0,
+	BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1,
+	BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2,
+	BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3,
+	BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4,
+	BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5,
+	BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6,
+	BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7,
+	BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8,
+	BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN = 9,
+	BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10,
+	BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
+	BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
+	BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
+	BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
+	BNXT_ULP_REGFILE_INDEX_LAST = 15
 };
 
 enum bnxt_ulp_resource_func {
@@ -179,7 +191,7 @@ enum bnxt_ulp_resource_func {
 enum bnxt_ulp_result_opc {
 	BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
 	BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
-	BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP_SZ = 2,
+	BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 2,
 	BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,
 	BNXT_ULP_RESULT_OPC_LAST = 4
 };
@@ -198,6 +210,45 @@ enum bnxt_ulp_spec_opc {
 	BNXT_ULP_SPEC_OPC_LAST = 4
 };
 
+enum bnxt_ulp_encap_vtag_encoding {
+	BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_ECAP_PRI = 4,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_REMAP_DIFFSERV = 5,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_ECAP_PRI = 6,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_DIFFSERV = 7,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_0 = 8,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_1 = 9,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_2 = 10,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_3 = 11,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_4 = 12,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_5 = 13,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_6 = 14,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_7 = 15,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_NOP = 0,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_ECAP_PRI = 1,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_IVLAN_PRI = 2,
+	BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_REMAP_DIFFSERV = 3
+};
+
+enum bnxt_ulp_fdb_resource_flags {
+	BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
+	BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
+};
+
+enum bnxt_ulp_fdb_type {
+	BNXT_ULP_FDB_TYPE_DEFAULT = 1,
+	BNXT_ULP_FDB_TYPE_REGULAR = 0
+};
+
+enum bnxt_ulp_flow_dir_bitmask {
+	BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000,
+	BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000
+};
+
+enum bnxt_ulp_match_type_bitmask {
+	BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000,
+	BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001
+};
+
 enum bnxt_ulp_sym {
 	BNXT_ULP_SYM_BIG_ENDIAN = 0,
 	BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
@@ -208,6 +259,10 @@ enum bnxt_ulp_sym {
 	BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
 	BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
 	BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
+	BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,
+	BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,
+	BNXT_ULP_SYM_ECV_L2_EN_NO = 0,
+	BNXT_ULP_SYM_ECV_L2_EN_YES = 1,
 	BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
 	BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
 	BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
@@ -224,6 +279,8 @@ enum bnxt_ulp_sym {
 	BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
 	BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
 	BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
+	BNXT_ULP_SYM_ECV_VALID_NO = 0,
+	BNXT_ULP_SYM_ECV_VALID_YES = 1,
 	BNXT_ULP_SYM_IP_PROTO_UDP = 17,
 	BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
 	BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
@@ -244,8 +301,15 @@ enum bnxt_ulp_sym {
 	BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
 	BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
 	BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
+	BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
+	BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
 	BNXT_ULP_SYM_NO = 0,
 	BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
+	BNXT_ULP_SYM_POP_VLAN_NO = 0,
+	BNXT_ULP_SYM_POP_VLAN_YES = 1,
+	BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
+	BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,
+	BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
 	BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
 	BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
 	BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
@@ -262,6 +326,7 @@ enum bnxt_ulp_sym {
 	BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
 	BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
 	BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
+	BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,
 	BNXT_ULP_SYM_YES = 1
 };
 
@@ -274,6 +339,7 @@ enum bnxt_ulp_act_prop_sz {
 	BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,
 	BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,
 	BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,
+	BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4,
 	BNXT_ULP_ACT_PROP_SZ_VNIC = 4,
 	BNXT_ULP_ACT_PROP_SZ_VPORT = 4,
 	BNXT_ULP_ACT_PROP_SZ_MARK = 4,
@@ -317,38 +383,46 @@ enum bnxt_ulp_act_prop_idx {
 	BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,
 	BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,
 	BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,
-	BNXT_ULP_ACT_PROP_IDX_VNIC = 32,
-	BNXT_ULP_ACT_PROP_IDX_VPORT = 36,
-	BNXT_ULP_ACT_PROP_IDX_MARK = 40,
-	BNXT_ULP_ACT_PROP_IDX_COUNT = 44,
-	BNXT_ULP_ACT_PROP_IDX_METER = 48,
-	BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 52,
-	BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 60,
-	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 68,
-	BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 72,
-	BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 76,
-	BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 80,
-	BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 84,
-	BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 88,
-	BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 104,
-	BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 120,
-	BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 124,
-	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 128,
-	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 132,
-	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 136,
-	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 140,
-	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 144,
-	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 148,
-	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 152,
-	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 156,
-	BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 160,
-	BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 166,
-	BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 172,
-	BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 180,
-	BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 212,
-	BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 228,
-	BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 232,
-	BNXT_ULP_ACT_PROP_IDX_LAST = 264
+	BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32,
+	BNXT_ULP_ACT_PROP_IDX_VNIC = 36,
+	BNXT_ULP_ACT_PROP_IDX_VPORT = 40,
+	BNXT_ULP_ACT_PROP_IDX_MARK = 44,
+	BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
+	BNXT_ULP_ACT_PROP_IDX_METER = 52,
+	BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
+	BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
+	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 72,
+	BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 76,
+	BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 80,
+	BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 84,
+	BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 88,
+	BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 92,
+	BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 108,
+	BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 124,
+	BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 128,
+	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 132,
+	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 136,
+	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 140,
+	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 144,
+	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 148,
+	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 152,
+	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 156,
+	BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 160,
+	BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 164,
+	BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 170,
+	BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 176,
+	BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 184,
+	BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 216,
+	BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 232,
+	BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236,
+	BNXT_ULP_ACT_PROP_IDX_LAST = 268
+};
+enum bnxt_ulp_class_hid {
+	BNXT_ULP_CLASS_HID_0092 = 0x0092
+};
+
+enum bnxt_ulp_act_hid {
+	BNXT_ULP_ACT_HID_0029 = 0x0029
 };
 
 #endif /* _ULP_TEMPLATE_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
index 1bc4449ab..587de8a83 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
@@ -1,130 +1,63 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2014-2020 Broadcom
- * All rights reserved_
+ * All rights reserved.
  */
 
-/* date: Mon Mar  9 02:37:53 2020
- * version: 0_0
- */
-
-#ifndef _ULP_HDR_FIELD_ENUMS_H_
-#define _ULP_HDR_FIELD_ENUMS_H_
+#ifndef ULP_HDR_FIELD_ENUMS_H_
+#define ULP_HDR_FIELD_ENUMS_H_
 
 enum bnxt_ulp_hf0 {
-	BNXT_ULP_HF0_MPLS_TAG_NUM = 0,
-	BNXT_ULP_HF0_O_VTAG_NUM = 1,
-	BNXT_ULP_HF0_I_VTAG_NUM = 2,
-	BNXT_ULP_HF0_SVIF_INDEX = 3,
-	BNXT_ULP_HF0_O_ETH_DMAC = 4,
-	BNXT_ULP_HF0_O_ETH_SMAC = 5,
-	BNXT_ULP_HF0_O_ETH_TYPE = 6,
-	BNXT_ULP_HF0_OO_VLAN_CFI_PRI = 7,
-	BNXT_ULP_HF0_OO_VLAN_VID = 8,
-	BNXT_ULP_HF0_OO_VLAN_TYPE = 9,
-	BNXT_ULP_HF0_OI_VLAN_CFI_PRI = 10,
-	BNXT_ULP_HF0_OI_VLAN_VID = 11,
-	BNXT_ULP_HF0_OI_VLAN_TYPE = 12,
-	BNXT_ULP_HF0_O_IPV4_VER = 13,
-	BNXT_ULP_HF0_O_IPV4_TOS = 14,
-	BNXT_ULP_HF0_O_IPV4_LEN = 15,
-	BNXT_ULP_HF0_O_IPV4_FRAG_ID = 16,
-	BNXT_ULP_HF0_O_IPV4_FRAG_OFF = 17,
-	BNXT_ULP_HF0_O_IPV4_TTL = 18,
-	BNXT_ULP_HF0_O_IPV4_NEXT_PID = 19,
-	BNXT_ULP_HF0_O_IPV4_CSUM = 20,
-	BNXT_ULP_HF0_O_IPV4_SRC_ADDR = 21,
-	BNXT_ULP_HF0_O_IPV4_DST_ADDR = 22,
-	BNXT_ULP_HF0_O_UDP_SRC_PORT = 23,
-	BNXT_ULP_HF0_O_UDP_DST_PORT = 24,
-	BNXT_ULP_HF0_O_UDP_LENGTH = 25,
-	BNXT_ULP_HF0_O_UDP_CSUM = 26,
-	BNXT_ULP_HF0_T_VXLAN_FLAGS = 27,
-	BNXT_ULP_HF0_T_VXLAN_RSVD0 = 28,
-	BNXT_ULP_HF0_T_VXLAN_VNI = 29,
-	BNXT_ULP_HF0_T_VXLAN_RSVD1 = 30,
-	BNXT_ULP_HF0_I_ETH_DMAC = 31,
-	BNXT_ULP_HF0_I_ETH_SMAC = 32,
-	BNXT_ULP_HF0_I_ETH_TYPE = 33,
-	BNXT_ULP_HF0_IO_VLAN_CFI_PRI = 34,
-	BNXT_ULP_HF0_IO_VLAN_VID = 35,
-	BNXT_ULP_HF0_IO_VLAN_TYPE = 36,
-	BNXT_ULP_HF0_II_VLAN_CFI_PRI = 37,
-	BNXT_ULP_HF0_II_VLAN_VID = 38,
-	BNXT_ULP_HF0_II_VLAN_TYPE = 39,
-	BNXT_ULP_HF0_I_IPV4_VER = 40,
-	BNXT_ULP_HF0_I_IPV4_TOS = 41,
-	BNXT_ULP_HF0_I_IPV4_LEN = 42,
-	BNXT_ULP_HF0_I_IPV4_FRAG_ID = 43,
-	BNXT_ULP_HF0_I_IPV4_FRAG_OFF = 44,
-	BNXT_ULP_HF0_I_IPV4_TTL = 45,
-	BNXT_ULP_HF0_I_IPV4_NEXT_PID = 46,
-	BNXT_ULP_HF0_I_IPV4_CSUM = 47,
-	BNXT_ULP_HF0_I_IPV4_SRC_ADDR = 48,
-	BNXT_ULP_HF0_I_IPV4_DST_ADDR = 49,
-	BNXT_ULP_HF0_I_UDP_SRC_PORT = 50,
-	BNXT_ULP_HF0_I_UDP_DST_PORT = 51,
-	BNXT_ULP_HF0_I_UDP_LENGTH = 52,
-	BNXT_ULP_HF0_I_UDP_CSUM = 53
-};
-
-enum bnxt_ulp_hf1 {
-	BNXT_ULP_HF1_MPLS_TAG_NUM = 0,
-	BNXT_ULP_HF1_O_VTAG_NUM = 1,
-	BNXT_ULP_HF1_I_VTAG_NUM = 2,
-	BNXT_ULP_HF1_SVIF_INDEX = 3,
-	BNXT_ULP_HF1_O_ETH_DMAC = 4,
-	BNXT_ULP_HF1_O_ETH_SMAC = 5,
-	BNXT_ULP_HF1_O_ETH_TYPE = 6,
-	BNXT_ULP_HF1_OO_VLAN_CFI_PRI = 7,
-	BNXT_ULP_HF1_OO_VLAN_VID = 8,
-	BNXT_ULP_HF1_OO_VLAN_TYPE = 9,
-	BNXT_ULP_HF1_OI_VLAN_CFI_PRI = 10,
-	BNXT_ULP_HF1_OI_VLAN_VID = 11,
-	BNXT_ULP_HF1_OI_VLAN_TYPE = 12,
-	BNXT_ULP_HF1_O_IPV4_VER = 13,
-	BNXT_ULP_HF1_O_IPV4_TOS = 14,
-	BNXT_ULP_HF1_O_IPV4_LEN = 15,
-	BNXT_ULP_HF1_O_IPV4_FRAG_ID = 16,
-	BNXT_ULP_HF1_O_IPV4_FRAG_OFF = 17,
-	BNXT_ULP_HF1_O_IPV4_TTL = 18,
-	BNXT_ULP_HF1_O_IPV4_NEXT_PID = 19,
-	BNXT_ULP_HF1_O_IPV4_CSUM = 20,
-	BNXT_ULP_HF1_O_IPV4_SRC_ADDR = 21,
-	BNXT_ULP_HF1_O_IPV4_DST_ADDR = 22,
-	BNXT_ULP_HF1_O_UDP_SRC_PORT = 23,
-	BNXT_ULP_HF1_O_UDP_DST_PORT = 24,
-	BNXT_ULP_HF1_O_UDP_LENGTH = 25,
-	BNXT_ULP_HF1_O_UDP_CSUM = 26
+	BNXT_ULP_HF0_IDX_SVIF_INDEX              = 0,
+	BNXT_ULP_HF0_IDX_O_ETH_DMAC              = 1,
+	BNXT_ULP_HF0_IDX_O_ETH_SMAC              = 2,
+	BNXT_ULP_HF0_IDX_O_ETH_TYPE              = 3,
+	BNXT_ULP_HF0_IDX_OO_VLAN_CFI_PRI         = 4,
+	BNXT_ULP_HF0_IDX_OO_VLAN_VID             = 5,
+	BNXT_ULP_HF0_IDX_OO_VLAN_TYPE            = 6,
+	BNXT_ULP_HF0_IDX_OI_VLAN_CFI_PRI         = 7,
+	BNXT_ULP_HF0_IDX_OI_VLAN_VID             = 8,
+	BNXT_ULP_HF0_IDX_OI_VLAN_TYPE            = 9,
+	BNXT_ULP_HF0_IDX_O_IPV4_VER              = 10,
+	BNXT_ULP_HF0_IDX_O_IPV4_TOS              = 11,
+	BNXT_ULP_HF0_IDX_O_IPV4_LEN              = 12,
+	BNXT_ULP_HF0_IDX_O_IPV4_FRAG_ID          = 13,
+	BNXT_ULP_HF0_IDX_O_IPV4_FRAG_OFF         = 14,
+	BNXT_ULP_HF0_IDX_O_IPV4_TTL              = 15,
+	BNXT_ULP_HF0_IDX_O_IPV4_NEXT_PID         = 16,
+	BNXT_ULP_HF0_IDX_O_IPV4_CSUM             = 17,
+	BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR         = 18,
+	BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR         = 19,
+	BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT          = 20,
+	BNXT_ULP_HF0_IDX_O_UDP_DST_PORT          = 21,
+	BNXT_ULP_HF0_IDX_O_UDP_LENGTH            = 22,
+	BNXT_ULP_HF0_IDX_O_UDP_CSUM              = 23
 };
 
-enum bnxt_ulp_hf2 {
-	BNXT_ULP_HF2_MPLS_TAG_NUM = 0,
-	BNXT_ULP_HF2_O_VTAG_NUM = 1,
-	BNXT_ULP_HF2_I_VTAG_NUM = 2,
-	BNXT_ULP_HF2_SVIF_INDEX = 3,
-	BNXT_ULP_HF2_O_ETH_DMAC = 4,
-	BNXT_ULP_HF2_O_ETH_SMAC = 5,
-	BNXT_ULP_HF2_O_ETH_TYPE = 6,
-	BNXT_ULP_HF2_OO_VLAN_CFI_PRI = 7,
-	BNXT_ULP_HF2_OO_VLAN_VID = 8,
-	BNXT_ULP_HF2_OO_VLAN_TYPE = 9,
-	BNXT_ULP_HF2_OI_VLAN_CFI_PRI = 10,
-	BNXT_ULP_HF2_OI_VLAN_VID = 11,
-	BNXT_ULP_HF2_OI_VLAN_TYPE = 12,
-	BNXT_ULP_HF2_O_IPV4_VER = 13,
-	BNXT_ULP_HF2_O_IPV4_TOS = 14,
-	BNXT_ULP_HF2_O_IPV4_LEN = 15,
-	BNXT_ULP_HF2_O_IPV4_FRAG_ID = 16,
-	BNXT_ULP_HF2_O_IPV4_FRAG_OFF = 17,
-	BNXT_ULP_HF2_O_IPV4_TTL = 18,
-	BNXT_ULP_HF2_O_IPV4_NEXT_PID = 19,
-	BNXT_ULP_HF2_O_IPV4_CSUM = 20,
-	BNXT_ULP_HF2_O_IPV4_SRC_ADDR = 21,
-	BNXT_ULP_HF2_O_IPV4_DST_ADDR = 22,
-	BNXT_ULP_HF2_O_UDP_SRC_PORT = 23,
-	BNXT_ULP_HF2_O_UDP_DST_PORT = 24,
-	BNXT_ULP_HF2_O_UDP_LENGTH = 25,
-	BNXT_ULP_HF2_O_UDP_CSUM = 26
+enum bnxt_ulp_hf_bitmask0 {
+	BNXT_ULP_HF0_BITMASK_SVIF_INDEX          = 0x8000000000000000,
+	BNXT_ULP_HF0_BITMASK_O_ETH_DMAC          = 0x4000000000000000,
+	BNXT_ULP_HF0_BITMASK_O_ETH_SMAC          = 0x2000000000000000,
+	BNXT_ULP_HF0_BITMASK_O_ETH_TYPE          = 0x1000000000000000,
+	BNXT_ULP_HF0_BITMASK_OO_VLAN_CFI_PRI     = 0x0800000000000000,
+	BNXT_ULP_HF0_BITMASK_OO_VLAN_VID         = 0x0400000000000000,
+	BNXT_ULP_HF0_BITMASK_OO_VLAN_TYPE        = 0x0200000000000000,
+	BNXT_ULP_HF0_BITMASK_OI_VLAN_CFI_PRI     = 0x0100000000000000,
+	BNXT_ULP_HF0_BITMASK_OI_VLAN_VID         = 0x0080000000000000,
+	BNXT_ULP_HF0_BITMASK_OI_VLAN_TYPE        = 0x0040000000000000,
+	BNXT_ULP_HF0_BITMASK_O_IPV4_VER          = 0x0020000000000000,
+	BNXT_ULP_HF0_BITMASK_O_IPV4_TOS          = 0x0010000000000000,
+	BNXT_ULP_HF0_BITMASK_O_IPV4_LEN          = 0x0008000000000000,
+	BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_ID      = 0x0004000000000000,
+	BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_OFF     = 0x0002000000000000,
+	BNXT_ULP_HF0_BITMASK_O_IPV4_TTL          = 0x0001000000000000,
+	BNXT_ULP_HF0_BITMASK_O_IPV4_NEXT_PID     = 0x0000800000000000,
+	BNXT_ULP_HF0_BITMASK_O_IPV4_CSUM         = 0x0000400000000000,
+	BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR     = 0x0000200000000000,
+	BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR     = 0x0000100000000000,
+	BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT      = 0x0000080000000000,
+	BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT      = 0x0000040000000000,
+	BNXT_ULP_HF0_BITMASK_O_UDP_LENGTH        = 0x0000020000000000,
+	BNXT_ULP_HF0_BITMASK_O_UDP_CSUM          = 0x0000010000000000
 };
 
 #endif /* _ULP_HDR_FIELD_ENUMS_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 8adbf7a24..c2d3ccb3e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -28,11 +28,16 @@
 #define BNXT_ULP_PROTO_HDR_TCP_NUM	9
 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM	4
 #define BNXT_ULP_PROTO_HDR_MAX		128
+#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX	0
 
 struct ulp_rte_hdr_bitmap {
 	uint64_t	bits;
 };
 
+struct ulp_rte_field_bitmap {
+	uint64_t	bits;
+};
+
 /* Structure to store the protocol fields */
 #define RTE_PARSER_FLOW_HDR_FIELD_SIZE		16
 struct ulp_rte_hdr_field {
@@ -53,7 +58,9 @@ struct ulp_rte_act_prop {
 /* Structure to be used for passing all the parser functions */
 struct ulp_rte_parser_params {
 	struct ulp_rte_hdr_bitmap	hdr_bitmap;
+	struct ulp_rte_field_bitmap	fld_bitmap;
 	struct ulp_rte_hdr_field	hdr_field[BNXT_ULP_PROTO_HDR_MAX];
+	uint32_t			comp_fld[BNXT_ULP_CHF_IDX_LAST];
 	uint32_t			field_idx;
 	uint32_t			vlan_idx;
 	struct ulp_rte_act_bitmap	act_bitmap;
@@ -72,11 +79,6 @@ struct bnxt_ulp_rte_hdr_info {
 /* Flow Parser Header Information Structure Array defined in template source*/
 extern struct bnxt_ulp_rte_hdr_info	ulp_hdr_info[];
 
-struct bnxt_ulp_matcher_field_info {
-	enum bnxt_ulp_fmf_mask	mask_opcode;
-	enum bnxt_ulp_fmf_spec	spec_opcode;
-};
-
 /* Flow Parser Action Information Structure */
 struct bnxt_ulp_rte_act_info {
 	enum bnxt_ulp_act_type					act_type;
@@ -98,12 +100,22 @@ struct bnxt_ulp_header_match_info {
 	uint32_t				act_vnic;
 };
 
-/* Flow Matcher templates Structure Array defined in template source*/
-extern struct bnxt_ulp_header_match_info  ulp_ingress_hdr_match_list[];
-extern struct bnxt_ulp_header_match_info  ulp_egress_hdr_match_list[];
+struct ulp_rte_bitmap {
+	uint64_t	bits;
+};
+
+struct bnxt_ulp_class_match_info {
+	struct ulp_rte_bitmap	hdr_sig;
+	struct ulp_rte_bitmap	field_sig;
+	uint32_t		class_hid;
+	uint32_t		class_tid;
+	uint8_t			act_vnic;
+	uint8_t			wc_pri;
+};
 
-/* Flow field match Information Structure Array defined in template source*/
-extern struct bnxt_ulp_matcher_field_info	ulp_field_match[];
+/* Flow Matcher templates Structure for class entries */
+extern uint16_t ulp_class_sig_tbl[];
+extern struct bnxt_ulp_class_match_info ulp_class_match_list[];
 
 /* Flow Matcher Action structures */
 struct bnxt_ulp_action_match_info {
@@ -111,9 +123,15 @@ struct bnxt_ulp_action_match_info {
 	uint32_t				act_tmpl_id;
 };
 
-/* Flow Matcher templates Structure Array defined in template source */
-extern struct bnxt_ulp_action_match_info  ulp_ingress_act_match_list[];
-extern struct bnxt_ulp_action_match_info  ulp_egress_act_match_list[];
+struct bnxt_ulp_act_match_info {
+	struct ulp_rte_bitmap	act_sig;
+	uint32_t		act_hid;
+	uint32_t		act_tid;
+};
+
+/* Flow Matcher templates Structure for action entries */
+extern	uint16_t ulp_act_sig_tbl[];
+extern struct bnxt_ulp_act_match_info ulp_act_match_list[];
 
 /* Device specific parameters */
 struct bnxt_ulp_device_params {
@@ -179,7 +197,7 @@ struct bnxt_ulp_mapper_act_tbl_info {
 };
 
 struct bnxt_ulp_mapper_class_key_field_info {
-	uint8_t			name[64];
+	uint8_t			description[64];
 	enum bnxt_ulp_mask_opc	mask_opcode;
 	enum bnxt_ulp_spec_opc	spec_opcode;
 	uint16_t		field_bit_size;
@@ -188,14 +206,14 @@ struct bnxt_ulp_mapper_class_key_field_info {
 };
 
 struct bnxt_ulp_mapper_result_field_info {
-	uint8_t				name[64];
+	uint8_t				description[64];
 	enum bnxt_ulp_result_opc	result_opcode;
 	uint16_t			field_bit_size;
 	uint8_t				result_operand[16];
 };
 
 struct bnxt_ulp_mapper_ident_info {
-	uint8_t		name[64];
+	uint8_t		description[64];
 	uint32_t	resource_func;
 
 	uint16_t	ident_type;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index e1d652864..0150c1d49 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -519,3 +519,36 @@ int32_t ulp_buffer_is_empty(const uint8_t *buf, uint32_t size)
 {
 	return buf[0] == 0 && !memcmp(buf, buf + 1, size - 1);
 }
+
+/* Function to check if bitmap is zero.Return 1 on success */
+uint32_t ulp_bitmap_is_zero(uint8_t *bitmap, int32_t size)
+{
+	while (size-- > 0) {
+		if (*bitmap != 0)
+			return 0;
+		bitmap++;
+	}
+	return 1;
+}
+
+/* Function to check if bitmap is ones. Return 1 on success */
+uint32_t ulp_bitmap_is_ones(uint8_t *bitmap, int32_t size)
+{
+	while (size-- > 0) {
+		if (*bitmap != 0xFF)
+			return 0;
+		bitmap++;
+	}
+	return 1;
+}
+
+/* Function to check if bitmap is not zero. Return 1 on success */
+uint32_t ulp_bitmap_notzero(uint8_t *bitmap, int32_t size)
+{
+	while (size-- > 0) {
+		if (*bitmap != 0)
+			return 1;
+		bitmap++;
+	}
+	return 0;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index f729ff681..5db393398 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -16,7 +16,7 @@
 #define ULP_BITMAP_SET(bitmap, val)	((bitmap) |= (val))
 #define ULP_BITMAP_RESET(bitmap, val)	((bitmap) &= ~(val))
 #define ULP_BITMAP_ISSET(bitmap, val)	((bitmap) & (val))
-#define ULP_BITSET_CMP(b1, b2)  memcmp(&(b1)->bits, \
+#define ULP_BITMAP_CMP(b1, b2)  memcmp(&(b1)->bits, \
 				&(b2)->bits, sizeof((b1)->bits))
 /*
  * Macros for bitmap sets and gets
@@ -50,6 +50,12 @@
 /* Macro to convert bits to bytes with no round off*/
 #define ULP_BITS_2_BYTE_NR(bits_x)	((bits_x) / 8)
 
+/* Macros to read the computed fields */
+#define ULP_UTIL_CHF_IDX_RD(params, idx) \
+	rte_be_to_cpu_32((params)->comp_fld[(idx)])
+
+#define ULP_UTIL_CHF_IDX_WR(params, idx, val)	\
+	((params)->comp_fld[(idx)] = rte_cpu_to_be_32((val)))
 /*
  * Making the blob statically sized to 128 bytes for now.
  * The blob must be initialized with ulp_blob_init prior to using.
@@ -276,4 +282,13 @@ ulp_encap_buffer_copy(uint8_t *dst,
  */
 int32_t ulp_buffer_is_empty(const uint8_t *buf, uint32_t size);
 
+/* Function to check if bitmap is zero.Return 1 on success */
+uint32_t ulp_bitmap_is_zero(uint8_t *bitmap, int32_t size);
+
+/* Function to check if bitmap is ones. Return 1 on success */
+uint32_t ulp_bitmap_is_ones(uint8_t *bitmap, int32_t size);
+
+/* Function to check if bitmap is not zero. Return 1 on success */
+uint32_t ulp_bitmap_notzero(uint8_t *bitmap, int32_t size);
+
 #endif /* _ULP_UTILS_H_ */
