From patchwork Wed Apr 1 14:21:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 67598 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B17AA057B; Wed, 1 Apr 2020 16:24:02 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C4F1A1C045; Wed, 1 Apr 2020 16:21:57 +0200 (CEST) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by dpdk.org (Postfix) with ESMTP id CBEAD1BF4F for ; Wed, 1 Apr 2020 16:21:55 +0200 (CEST) Received: by mail-lj1-f193.google.com with SMTP id b1so5389744ljp.3 for ; Wed, 01 Apr 2020 07:21:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nlLsOBxFZOP6jpzMwj14vEMzQXXfKXh8UF45x0bBkf8=; b=alipajx0GmcDKGaa0qBMoXqqu1ixrKfLSun+HPaxrxTT/bUDr5HHk6q3cPpXsRd9hD BqUg0MruVp4B3x/lS56bjAk+09liMIckyWCSZgVpiDe35FOI2jEWZ83skcoeJ9WEk+jj ziTE/2q8qg4rfaQSK4BefcwSyf1pRnqpsDDFuTnup22vzGFRa+TQ3/icEZqDiMJx6nbP OPchsSKMYVh960XyPkrqB7+XSepxbaF+ACoKiJ4yrE0BTriQsJgJaRsET0YyqKXQzP5x e4W9snD9cTI2YO6yg/1e0gc/MC+gplPDnwwC62eBCsk/fTAoEg5ORUNClzdrN1TKjkTB Q3jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nlLsOBxFZOP6jpzMwj14vEMzQXXfKXh8UF45x0bBkf8=; b=DMeUYmS7OlcME/yYs0TMXYywtSQc/4LA2lfaMEajpeQW0qcwsnvKb639Esx/hm9APY zPo/evQdF7NQHJ9BxVzVREVDZe58Puv12/tRhVC1h9hTzKOC3rCZeqcD7EV9zIrRooYP r5iBM2IvPS6sCaOmENQA9japwNIMGXpnM8lCcH7X1/aDSeIUHNs3XEbxKXf8KZpsNtuH FkLc7oYUlXjNfznjQFGzOOOZdp+XW4Z/5hYimeRkG2FRIIEc6SJ+RJufV0k6XygiCoW2 zBSWp9x4SHL3K3y5CWLjZo97mWmMXmmBXxHCLTPT0vcZ9Sg9lahBWaEYYU5c6hgRLh8x YURg== X-Gm-Message-State: AGi0PuYEFCa5snBFHWAhtnUtLW39OTESb4Kh4Fv1QSuRmdjnAKE3nlC/ oyirKqsaiJS/zq1R7X4kZZAoKqpcJzk= X-Google-Smtp-Source: APiQypKlyJWnEcawmyHkd6hDpV43DORnpKDAjGaz5ZvKdYnrutrnQPHDmQIT3tFYq4fYdA6BHW9FFQ== X-Received: by 2002:a2e:8795:: with SMTP id n21mr13752700lji.71.1585750915226; Wed, 01 Apr 2020 07:21:55 -0700 (PDT) Received: from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2020 07:21:54 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, Michal Krawczyk Date: Wed, 1 Apr 2020 16:21:11 +0200 Message-Id: <20200401142127.13715-14-mk@semihalf.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200401142127.13715-1-mk@semihalf.com> References: <20200401142127.13715-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 13/29] net/ena/base: fix indentation of multiple defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As the alignemnt of the defines wasn't valid, it was removed at all, so instead of using multiple spaces or tabs, the single space after define name is being used. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index 9b87fa94e4..274c0cd9f5 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -8,9 +8,9 @@ #include "ena_plat.h" -#define ENA_MAX_NUM_IO_QUEUES 128U +#define ENA_MAX_NUM_IO_QUEUES 128U /* We need to queues for each IO (on for Tx and one for Rx) */ -#define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) +#define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) #define ENA_MAX_HANDLERS 256 @@ -33,9 +33,9 @@ #define ENA_HASH_KEY_SIZE 40 -#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF +#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF -#define ENA_FEATURE_MAX_QUEUE_EXT_VER 1 +#define ENA_FEATURE_MAX_QUEUE_EXT_VER 1 struct ena_llq_configurations { enum ena_admin_llq_header_location llq_header_location;