diff mbox series

[10/10] net/enetc: init SI transactions attribute reg

Message ID 20200302143209.11854-11-hemant.agrawal@nxp.com (mailing list archive)
State Accepted, archived
Delegated to: Ferruh Yigit
Headers
Series net/enetc: optimization and cleanup |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/travis-robot success Travis build: passed
ci/Intel-compilation success Compilation OK

Commit Message

Hemant Agrawal March 2, 2020, 2:32 p.m. UTC 
  From: Alex Marginean <alexandru.marginean@nxp.com>

This was left to its default value.  With the patch transactions are:
- coherent,
- do not allocate in downstream cache (there is none on LS1028a),
- merge surrounding data for BD writes,
- overwrite surrounding data for frame data writes.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
---
 drivers/net/enetc/base/enetc_hw.h | 2 ++
 drivers/net/enetc/enetc_ethdev.c  | 6 ++++++
 2 files changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/enetc/base/enetc_hw.h b/drivers/net/enetc/base/enetc_hw.h
index 00813284e..66fad58e5 100644
--- a/drivers/net/enetc/base/enetc_hw.h
+++ b/drivers/net/enetc/base/enetc_hw.h
@@ -22,6 +22,8 @@ 
 #define ENETC_SIMR			0x0
 #define ENETC_SIMR_EN			BIT(31)
 
+#define ENETC_SICAR0			0x40
+#define ENETC_SICAR0_COHERENT		0x2B2B6727
 #define ENETC_SIPMAR0			0x80
 #define ENETC_SIPMAR1			0x84
 
diff --git a/drivers/net/enetc/enetc_ethdev.c b/drivers/net/enetc/enetc_ethdev.c
index eb637d030..1716e11dd 100644
--- a/drivers/net/enetc/enetc_ethdev.c
+++ b/drivers/net/enetc/enetc_ethdev.c
@@ -150,6 +150,12 @@  enetc_hardware_init(struct enetc_eth_hw *hw)
 	/* WA for Rx lock-up HW erratum */
 	enetc_port_wr(enetc_hw, ENETC_PM0_RX_FIFO, 1);
 
+	/* set ENETC transaction flags to coherent, don't allocate.
+	 * BD writes merge with surrounding cache line data, frame data writes
+	 * overwrite cache line.
+	 */
+	enetc_wr(enetc_hw, ENETC_SICAR0, ENETC_SICAR0_COHERENT);
+
 	/* Enabling Station Interface */
 	enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN);