From patchwork Mon Sep 2 12:17:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 58390 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 52DC31E949; Mon, 2 Sep 2019 14:32:35 +0200 (CEST) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 7143F1D155 for ; Mon, 2 Sep 2019 14:32:08 +0200 (CEST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 5494F1A0697; Mon, 2 Sep 2019 14:32:08 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 7F91D1A02F6; Mon, 2 Sep 2019 14:32:06 +0200 (CEST) Received: from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 4BF194032A; Mon, 2 Sep 2019 20:32:02 +0800 (SGT) From: Akhil Goyal To: dev@dpdk.org Cc: hemant.agrawal@nxp.com, vakul.garg@nxp.com Date: Mon, 2 Sep 2019 17:47:24 +0530 Message-Id: <20190902121734.926-11-akhil.goyal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190902121734.926-1-akhil.goyal@nxp.com> References: <20190902121734.926-1-akhil.goyal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH 10/20] crypto/dpaa2_sec: disable 'write-safe' for PDCP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vakul Garg PDCP descriptors in some cases internally use commands which overwrite memory with extra '0s' if write-safe is kept enabled. This breaks correct functional behavior of PDCP apis and they in many cases give incorrect crypto output. There we disable 'write-safe' bit in FLC for PDCP cases. If there is a performance drop, then write-safe would be enabled selectively through a separate patch. Signed-off-by: Vakul Garg Acked-by: Akhil Goyal --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index cbc7dff04..c9029e989 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -2899,8 +2899,12 @@ dpaa2_sec_set_pdcp_session(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; - /* Set EWS bit i.e. enable write-safe */ - DPAA2_SET_FLC_EWS(flc); + /* TODO - check the perf impact or + * align as per descriptor type + * Set EWS bit i.e. enable write-safe + * DPAA2_SET_FLC_EWS(flc); + */ + /* Set BS = 1 i.e reuse input buffers as output buffers */ DPAA2_SET_FLC_REUSE_BS(flc); /* Set FF = 10; reuse input buffers if they provide sufficient space */