diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 7d1fead..bee56ab 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -15,6 +15,7 @@ Supported OCTEON TX2 SoCs
 
 - CN96xx
 - CN93xx
+- CNF95xx
 
 OCTEON TX2 Resource Virtualization Unit architecture
 ----------------------------------------------------
diff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h
index cdb25d9..faf206b 100644
--- a/drivers/common/octeontx2/otx2_common.h
+++ b/drivers/common/octeontx2/otx2_common.h
@@ -108,6 +108,26 @@ extern int otx2_logtype_dpi;
 #define PCI_DEVID_OCTEONTX2_RVU_AF_VF		0xA0f8
 #define PCI_DEVID_OCTEONTX2_DPI_VF		0xA081
 
+/* Subsystem Device ID */
+#define PCI_SUBSYS_DEVID_96XX_95XX		0xB200
+
+/*
+ * REVID for RVU PCIe devices.
+ * Bits 0..1: minor pass
+ * Bits 3..2: major pass
+ * Bits 7..4: midr id, 0:96, 1:95, 2:loki, f:unknown
+ */
+
+#define RVU_PCI_REV_MIDR_ID(rev_id)		(rev_id >> 4)
+#define RVU_PCI_REV_MAJOR(rev_id)		((rev_id >> 2) & 0x3)
+#define RVU_PCI_REV_MINOR(rev_id)		(rev_id & 0x3)
+
+#define RVU_PCI_CN96XX_MIDR_ID			0x0
+#define RVU_PCI_CNF95XX_MIDR_ID			0x1
+
+/* PCI Config offsets */
+#define RVU_PCI_REVISION_ID			0x08
+
 /* IO Access */
 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
diff --git a/drivers/common/octeontx2/otx2_dev.c b/drivers/common/octeontx2/otx2_dev.c
index 3b51fa9..1478c95 100644
--- a/drivers/common/octeontx2/otx2_dev.c
+++ b/drivers/common/octeontx2/otx2_dev.c
@@ -876,12 +876,14 @@ otx2_dev_active_vfs(void *otx2_dev)
 }
 
 static void
-otx2_update_pass_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+otx2_update_pass_hwcap(struct rte_pci_device *pci_dev,
+		       struct otx2_dev *dev, uint8_t rev_id)
 {
-	RTE_SET_USED(pci_dev);
+	if (pci_dev->id.subsystem_device_id != PCI_SUBSYS_DEVID_96XX_95XX)
+		return;
 
-	/* Update this logic when we have A1 */
-	dev->hwcap |= OTX2_HWCAP_F_A0;
+	/* LSB contains rev_id */
+	dev->hwcap |= (uint64_t)rev_id;
 }
 
 static void
@@ -907,7 +909,8 @@ otx2_update_vf_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
  * Initialize the otx2 device
  */
 int
-otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)
+otx2_dev_init(struct rte_pci_device *pci_dev,
+	      void *otx2_dev, uint8_t rev_id)
 {
 	int up_direction = MBOX_DIR_PFAF_UP;
 	int rc, direction = MBOX_DIR_PFAF;
@@ -931,7 +934,7 @@ otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)
 	dev->bar4 = bar4;
 
 	otx2_update_vf_hwcap(pci_dev, dev);
-	otx2_update_pass_hwcap(pci_dev, dev);
+	otx2_update_pass_hwcap(pci_dev, dev, rev_id);
 
 	if (otx2_dev_is_vf(dev)) {
 		direction = MBOX_DIR_VFPF;
diff --git a/drivers/common/octeontx2/otx2_dev.h b/drivers/common/octeontx2/otx2_dev.h
index be862ad..de0fa0f 100644
--- a/drivers/common/octeontx2/otx2_dev.h
+++ b/drivers/common/octeontx2/otx2_dev.h
@@ -13,14 +13,18 @@
 #include "otx2_mempool.h"
 
 /* Common HWCAP flags. Use from LSB bits */
-#define OTX2_HWCAP_F_VF		BIT_ULL(0) /* VF device */
+#define OTX2_HWCAP_F_VF		BIT_ULL(8) /* VF device */
 #define otx2_dev_is_vf(dev)	(dev->hwcap & OTX2_HWCAP_F_VF)
 #define otx2_dev_is_pf(dev)	(!(dev->hwcap & OTX2_HWCAP_F_VF))
 #define otx2_dev_is_lbk(dev)	((dev->hwcap & OTX2_HWCAP_F_VF) && \
 				 (dev->tx_chan_base < 0x700))
+#define otx2_dev_revid(dev)	(dev->hwcap & 0xFF)
 
-#define OTX2_HWCAP_F_A0		BIT_ULL(1) /* A0 device */
-#define otx2_dev_is_A0(dev)	(dev->hwcap & OTX2_HWCAP_F_A0)
+#define otx2_dev_is_A0(dev)					\
+	((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&	\
+	 (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0))
+#define otx2_dev_is_Ax(dev)					\
+	((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0))
 
 struct otx2_dev;
 
@@ -61,7 +65,8 @@ struct otx2_dev {
 	OTX2_DEV;
 };
 
-int otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev);
+int otx2_dev_init(struct rte_pci_device *pci_dev,
+		  void *otx2_dev, uint8_t rev_id);
 void otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev);
 int otx2_dev_active_vfs(void *otx2_dev);
 
diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c
index 56716c2..cdee78b 100644
--- a/drivers/event/octeontx2/otx2_evdev.c
+++ b/drivers/event/octeontx2/otx2_evdev.c
@@ -1641,6 +1641,7 @@ otx2_sso_init(struct rte_eventdev *event_dev)
 	struct free_rsrcs_rsp *rsrc_cnt;
 	struct rte_pci_device *pci_dev;
 	struct otx2_sso_evdev *dev;
+	uint8_t rev_id;
 	int rc;
 
 	event_dev->dev_ops = &otx2_sso_ops;
@@ -1653,9 +1654,14 @@ otx2_sso_init(struct rte_eventdev *event_dev)
 	dev = sso_pmd_priv(event_dev);
 
 	pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
+	rc = rte_pci_read_config(pci_dev, &rev_id, 1, RVU_PCI_REVISION_ID);
+	if (rc != 1) {
+		otx2_err("Failed to read pci revision id, rc=%d", rc);
+		goto error;
+	}
 
 	/* Initialize the base otx2_dev object */
-	rc = otx2_dev_init(pci_dev, dev);
+	rc = otx2_dev_init(pci_dev, dev, rev_id);
 	if (rc < 0) {
 		otx2_err("Failed to initialize otx2_dev rc=%d", rc);
 		goto error;
diff --git a/drivers/mempool/octeontx2/otx2_mempool.c b/drivers/mempool/octeontx2/otx2_mempool.c
index 9a5f11c..e1c898d 100644
--- a/drivers/mempool/octeontx2/otx2_mempool.c
+++ b/drivers/mempool/octeontx2/otx2_mempool.c
@@ -344,6 +344,7 @@ otx2_npa_init(struct rte_pci_device *pci_dev)
 	const struct rte_memzone *mz;
 	struct otx2_dev *dev;
 	int rc = -ENOMEM;
+	uint8_t rev_id;
 
 	mz = rte_memzone_reserve_aligned(otx2_npa_dev_to_name(pci_dev, name),
 					 sizeof(*dev), SOCKET_ID_ANY,
@@ -353,8 +354,14 @@ otx2_npa_init(struct rte_pci_device *pci_dev)
 
 	dev = mz->addr;
 
+	rc = rte_pci_read_config(pci_dev, &rev_id, 1, RVU_PCI_REVISION_ID);
+	if (rc != 1) {
+		otx2_err("Failed to read pci revision id, rc=%d", rc);
+		goto malloc_fail;
+	}
+
 	/* Initialize the base otx2_dev object */
-	rc = otx2_dev_init(pci_dev, dev);
+	rc = otx2_dev_init(pci_dev, dev, rev_id);
 	if (rc)
 		goto malloc_fail;
 
diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index 156e7d3..5a9bb86 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -1235,7 +1235,7 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
 		nix_lf_free(dev);
 	}
 
-	if (otx2_dev_is_A0(dev) &&
+	if (otx2_dev_is_Ax(dev) &&
 	    (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
 	    ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
 	    (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
@@ -1681,6 +1681,7 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
 	struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
 	struct rte_pci_device *pci_dev;
 	int rc, max_entries;
+	uint8_t rev_id;
 
 	eth_dev->dev_ops = &otx2_eth_dev_ops;
 
@@ -1709,10 +1710,17 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
 	}
 
 	if (!dev->mbox_active) {
+		rc = rte_pci_read_config(pci_dev, &rev_id,
+					 1, RVU_PCI_REVISION_ID);
+		if (rc != 1) {
+			otx2_err("Failed to read pci revision id, rc=%d", rc);
+			goto error;
+		}
+
 		/* Initialize the base otx2_dev object
 		 * only if already present
 		 */
-		rc = otx2_dev_init(pci_dev, dev);
+		rc = otx2_dev_init(pci_dev, dev, rev_id);
 		if (rc) {
 			otx2_err("Failed to initialize otx2_dev rc=%d", rc);
 			goto error;
@@ -1787,7 +1795,7 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
 	dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
 	dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
 
-	if (otx2_dev_is_A0(dev)) {
+	if (otx2_dev_is_Ax(dev)) {
 		dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
 		dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
 	}
diff --git a/drivers/net/octeontx2/otx2_flow_ctrl.c b/drivers/net/octeontx2/otx2_flow_ctrl.c
index 0392086..ae56352 100644
--- a/drivers/net/octeontx2/otx2_flow_ctrl.c
+++ b/drivers/net/octeontx2/otx2_flow_ctrl.c
@@ -162,8 +162,8 @@ otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 
 	/* Check if TX pause frame is already enabled or not */
 	if (fc->tx_pause ^ tx_pause) {
-		if (otx2_dev_is_A0(dev) && eth_dev->data->dev_started) {
-			/* on A0, CQ should be in disabled state
+		if (otx2_dev_is_Ax(dev) && eth_dev->data->dev_started) {
+			/* on Ax, CQ should be in disabled state
 			 * while setting flow control configuration.
 			 */
 			otx2_info("Stop the port=%d for setting flow control\n",
@@ -207,8 +207,8 @@ otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev)
 	 */
 	otx2_nix_flow_ctrl_get(eth_dev, &fc_conf);
 
-	/* To avoid Link credit deadlock on A0, disable Tx FC if it's enabled */
-	if (otx2_dev_is_A0(dev) &&
+	/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
+	if (otx2_dev_is_Ax(dev) &&
 	    (fc_conf.mode == RTE_FC_FULL || fc_conf.mode == RTE_FC_RX_PAUSE)) {
 		fc_conf.mode =
 				(fc_conf.mode == RTE_FC_FULL ||
diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c
index 2469206..12903ec 100644
--- a/drivers/net/octeontx2/otx2_tm.c
+++ b/drivers/net/octeontx2/otx2_tm.c
@@ -59,7 +59,7 @@ static bool
 nix_tm_have_tl1_access(struct otx2_eth_dev *dev)
 {
 	bool is_lbk = otx2_dev_is_lbk(dev);
-	return otx2_dev_is_pf(dev) && !otx2_dev_is_A0(dev) &&
+	return otx2_dev_is_pf(dev) && !otx2_dev_is_Ax(dev) &&
 		!is_lbk && !dev->maxvf;
 }
 
