From patchwork Fri Jun 28 18:23:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 55636 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9AA801BB15; Fri, 28 Jun 2019 20:25:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 3AC8D1BA56 for ; Fri, 28 Jun 2019 20:25:15 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5SIPEFm014540; Fri, 28 Jun 2019 11:25:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=9HUwf3YZ5dcDN44ksUF0KovFQY44NdECnh05FQWW4vk=; b=aioj/m1bPhZCw5le2dFcJJm6/pgsgu21Ot9+/cGPFwfAS9YQ3/RyJDDThGOdsUUExpyK 1KUXvNjserhahqux+duLIXIZPhdcUB1tenKT/hEwOzuaMVd45hJ7HGduLePVZeFArmZA UvaGmNqCZoe3VVImzCRZjt3/wyXiTYVihVfyi0JvJC0Yodn5t5x9ltch0J0mfrwKGIA2 TzhGs2/0dvLU5NCQKFjQeriypA20Y5dltReTR0VeG9UjsR/1HohtEjutGL6edxUtjrCV 9aYRduNLjxY2RL5+vzmJaX4DwnkBo59G/OYEasLxt16r/qnAi7LTuZF0xGiXMGAFJVSM CQ== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2tdkg191m9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2019 11:25:14 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 28 Jun 2019 11:25:11 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 28 Jun 2019 11:25:11 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.12]) by maili.marvell.com (Postfix) with ESMTP id 2D7E13F7040; Fri, 28 Jun 2019 11:25:09 -0700 (PDT) From: To: , Pavan Nikhilesh , "John McNamara" , Marko Kovacevic CC: Date: Fri, 28 Jun 2019 23:53:42 +0530 Message-ID: <20190628182354.228-32-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190628182354.228-1-pbhagavatula@marvell.com> References: <20190628182354.228-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-28_08:, , signatures=0 Subject: [dpdk-dev] [PATCH v3 31/42] event/octeontx2: add devargs to modify chunk slots X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add devargs support to modify number of chunk slots. Chunks are used to store event timers, a chunk can be visualised as an array where the last element points to the next chunk and rest of them are used to store events. TIM traverses the list of chunks and enqueues the event timers to SSO. If no argument is passed then a default value of 255 is taken. Example: --dev "0002:0e:00.0,tim_chnk_slots=511" Signed-off-by: Pavan Nikhilesh --- doc/guides/eventdevs/octeontx2.rst | 11 +++++++++++ drivers/event/octeontx2/otx2_tim_evdev.c | 14 +++++++++++++- drivers/event/octeontx2/otx2_tim_evdev.h | 4 ++++ 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst index d24f81629..1e79bd916 100644 --- a/doc/guides/eventdevs/octeontx2.rst +++ b/doc/guides/eventdevs/octeontx2.rst @@ -103,6 +103,17 @@ Runtime Config Options --dev "0002:0e:00.0,tim_disable_npa=1" +- ``TIM modify chunk slots`` + + The ``tim_chnk_slots`` devargs can be used to modify number of chunk slots. + Chunks are used to store event timers, a chunk can be visualised as an array + where the last element points to the next chunk and rest of them are used to + store events. TIM traverses the list of chunks and enqueues the event timers + to SSO. The default value is 255 and the max value is 4095. + For example:: + + --dev "0002:0e:00.0,tim_chnk_slots=1023" + Debugging Options ~~~~~~~~~~~~~~~~~ diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index 4b9816676..c0a692bb5 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -240,7 +240,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10); tim_ring->max_tout = rcfg->max_tmo_ns; tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec); - tim_ring->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ; + tim_ring->chunk_sz = dev->chunk_sz; nb_timers = rcfg->nb_timers; tim_ring->disable_npa = dev->disable_npa; @@ -355,6 +355,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, } #define OTX2_TIM_DISABLE_NPA "tim_disable_npa" +#define OTX2_TIM_CHNK_SLOTS "tim_chnk_slots" static void tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev) @@ -370,6 +371,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev) rte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA, &parse_kvargs_flag, &dev->disable_npa); + rte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS, + &parse_kvargs_value, &dev->chunk_slots); } void @@ -423,6 +426,15 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev) goto mz_free; } + if (dev->chunk_slots && + dev->chunk_slots <= OTX2_TIM_MAX_CHUNK_SLOTS && + dev->chunk_slots >= OTX2_TIM_MIN_CHUNK_SLOTS) { + dev->chunk_sz = (dev->chunk_slots + 1) * + OTX2_TIM_CHUNK_ALIGNMENT; + } else { + dev->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ; + } + return; mz_free: diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index 0a0a0b4d8..9636d8414 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -22,6 +22,8 @@ #define OTX2_TIM_RING_DEF_CHUNK_SZ (4096) #define OTX2_TIM_CHUNK_ALIGNMENT (16) #define OTX2_TIM_NB_CHUNK_SLOTS(sz) (((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1) +#define OTX2_TIM_MIN_CHUNK_SLOTS (0x1) +#define OTX2_TIM_MAX_CHUNK_SLOTS (0x1FFE) #define OTX2_TIM_MIN_TMO_TKS (256) enum otx2_tim_clk_src { @@ -54,9 +56,11 @@ struct otx2_tim_evdev { struct rte_eventdev *event_dev; struct otx2_mbox *mbox; uint16_t nb_rings; + uint32_t chunk_sz; uintptr_t bar2; /* Dev args */ uint8_t disable_npa; + uint16_t chunk_slots; }; struct otx2_tim_ring {