From patchwork Fri Jun 28 07:50:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 55569 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D11E61BACE; Fri, 28 Jun 2019 09:52:40 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id BFDF61B974 for ; Fri, 28 Jun 2019 09:51:40 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5S7niS2000486 for ; Fri, 28 Jun 2019 00:51:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=Iswh/8zCaBwxGy0V0py+xjrGnSZFncti8IMsdOyM1AU=; b=ewYKZyWVvRYAErI3CewwubfkdainRgSULRgTWk80f+srzFBDH0YRo2I/b01qz0gHEwyJ tncG99dyCNnZBxrGCG+bA4HJQmGQmW7cFFriC5yDaQ+DhGxXyzEzlYcdaVOjOFLXl/dN vHReRnJ0wr9qqsfFlIE1y2pbWr7g7PByleK8hVT5hRWSYVaXgSdp96kfCLf1Pk7iMg4y pDbJyD7J22kzle95mKMQsAvdvgXKGLbbuym1rk554aLOcHQaW+rNVtVSMvbE5gbRrthB ZSFYCO4tPvF2JewLK51mk4yHc64/Yu4BtzE/PVe6oTglPiTe6uK4whkHU2uy8cNJDq/o wA== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0a-0016f401.pphosted.com with ESMTP id 2tdd778atu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 28 Jun 2019 00:51:39 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 28 Jun 2019 00:51:38 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 28 Jun 2019 00:51:38 -0700 Received: from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255]) by maili.marvell.com (Postfix) with ESMTP id C24FB3F7040; Fri, 28 Jun 2019 00:51:37 -0700 (PDT) From: To: CC: , Pavan Nikhilesh Date: Fri, 28 Jun 2019 13:20:13 +0530 Message-ID: <20190628075024.404-35-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190628075024.404-1-pbhagavatula@marvell.com> References: <20190628075024.404-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-28_02:, , signatures=0 Subject: [dpdk-dev] [PATCH v2 34/44] event/octeontx2: allow adapters to resize inflight buffers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add internal SSO functions to allow event adapters to resize SSO buffers that are used to hold in-flight events in DRAM. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/Makefile | 1 + drivers/event/octeontx2/meson.build | 1 + drivers/event/octeontx2/otx2_evdev.c | 31 ++++++++++++++++++++++ drivers/event/octeontx2/otx2_evdev.h | 5 ++++ drivers/event/octeontx2/otx2_evdev_adptr.c | 19 +++++++++++++ drivers/event/octeontx2/otx2_tim_evdev.c | 5 ++++ 6 files changed, 62 insertions(+) create mode 100644 drivers/event/octeontx2/otx2_evdev_adptr.c diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile index 2290622dd..6f8d9fe2f 100644 --- a/drivers/event/octeontx2/Makefile +++ b/drivers/event/octeontx2/Makefile @@ -33,6 +33,7 @@ LIBABIVER := 1 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_worker_dual.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_worker.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev_adptr.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_tim_evdev.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev_selftest.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev_irq.c diff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build index ad7f2e084..c709b5e69 100644 --- a/drivers/event/octeontx2/meson.build +++ b/drivers/event/octeontx2/meson.build @@ -5,6 +5,7 @@ sources = files('otx2_worker.c', 'otx2_worker_dual.c', 'otx2_evdev.c', + 'otx2_evdev_adptr.c', 'otx2_evdev_irq.c', 'otx2_evdev_selftest.c', 'otx2_tim_evdev.c', diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index a1222b3cf..914869b6c 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -529,6 +529,9 @@ sso_xaq_allocate(struct otx2_sso_evdev *dev) xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT; if (dev->xae_cnt) xaq_cnt += dev->xae_cnt / dev->xae_waes; + else if (dev->adptr_xae_cnt) + xaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) + + (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues); else xaq_cnt += (dev->iue / dev->xae_waes) + (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues); @@ -1030,6 +1033,34 @@ sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable) otx2_mbox_process(dev->mbox); } +int +sso_xae_reconfigure(struct rte_eventdev *event_dev) +{ + struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev); + struct rte_mempool *prev_xaq_pool; + int rc = 0; + + if (event_dev->data->dev_started) + sso_cleanup(event_dev, 0); + + prev_xaq_pool = dev->xaq_pool; + dev->xaq_pool = NULL; + sso_xaq_allocate(dev); + rc = sso_ggrp_alloc_xaq(dev); + if (rc < 0) { + otx2_err("Failed to alloc xaq to ggrp %d", rc); + rte_mempool_free(prev_xaq_pool); + return rc; + } + + rte_mempool_free(prev_xaq_pool); + rte_mb(); + if (event_dev->data->dev_started) + sso_cleanup(event_dev, 1); + + return 0; +} + static int otx2_sso_start(struct rte_eventdev *event_dev) { diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index 1e15b7e1c..ba3aae5ba 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -129,6 +129,7 @@ struct otx2_sso_evdev { uint64_t nb_xaq_cfg; rte_iova_t fc_iova; struct rte_mempool *xaq_pool; + uint32_t adptr_xae_cnt; /* Dev args */ uint8_t dual_ws; uint8_t selftest; @@ -243,6 +244,10 @@ uint16_t otx2_ssogws_dual_deq_timeout(void *port, struct rte_event *ev, uint16_t otx2_ssogws_dual_deq_timeout_burst(void *port, struct rte_event ev[], uint16_t nb_events, uint64_t timeout_ticks); + +void sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data, + uint32_t event_type); +int sso_xae_reconfigure(struct rte_eventdev *event_dev); void sso_fastpath_fns_set(struct rte_eventdev *event_dev); /* Clean up API's */ typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev); diff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c new file mode 100644 index 000000000..810722f89 --- /dev/null +++ b/drivers/event/octeontx2/otx2_evdev_adptr.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include "otx2_evdev.h" + +void +sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data, uint32_t event_type) +{ + switch (event_type) { + case RTE_EVENT_TYPE_TIMER: + { + dev->adptr_xae_cnt += (*(uint64_t *)data); + break; + } + default: + break; + } +} diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index 8324ded51..186c5d483 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -314,6 +314,11 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->base + TIM_LF_RING_BASE); otx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA); + /* Update SSO xae count. */ + sso_updt_xae_cnt(sso_pmd_priv(dev->event_dev), (void *)&nb_timers, + RTE_EVENT_TYPE_TIMER); + sso_xae_reconfigure(dev->event_dev); + return rc; chnk_mem_err: