From patchwork Sun Jun 2 15:24:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54104 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 690CF1BAE4; Sun, 2 Jun 2019 17:26:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 9F9601BACE for ; Sun, 2 Jun 2019 17:26:10 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x52FKK4k020364; Sun, 2 Jun 2019 08:26:10 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=UdX/E1T53oNXe8WvwAJIbJhI/clmkjV54i0L7JoKxPk=; b=qtM0O/w13Qh7vF2hxwrQ3G4cY1WQCk1w7YdQfLQCQfjxQ2e/QeYoPUknRIVJgRozS2xx VYhmzB5obvRpnvs6PKB3g67Ks3EBbPRjKXt8bx0Ch7pWuyer6ydqygBshoUtjD2jvy16 pfHjFVz4ZHTV6brQjKfmgZ03Ymn3foDQu6Nb4egWYoV84mMuRQKEoMv4LwDDYQSnzQx2 gtnntP1WmswWHanZF1IgpkgfjV/i7XQizs6RL4NJSCPf68NiB+efKewOOvHcEfk5/eoB 3vCmP1G2+xqDbOFyF0CRaItBa0uM3AgwK10z5yJ8r5liNVMxhYfW903tX+SaTn5UebeP JA== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk496a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 02 Jun 2019 08:26:09 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 2 Jun 2019 08:26:08 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sun, 2 Jun 2019 08:26:08 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 0B8ED3F703F; Sun, 2 Jun 2019 08:26:05 -0700 (PDT) From: To: , John McNamara , Marko Kovacevic , Jerin Jacob , "Nithin Dabilpuram" , Kiran Kumar K CC: , Vamsi Attunuru Date: Sun, 2 Jun 2019 20:54:06 +0530 Message-ID: <20190602152434.23996-31-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190602152434.23996-1-jerinj@marvell.com> References: <20190602152434.23996-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-02_09:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 30/58] net/octeontx2: add flow control support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vamsi Attunuru Add flow control operations and exposed otx2_nix_update_flow_ctrl_mode() to enable on the configured mode in dev_start(). Signed-off-by: Vamsi Attunuru Signed-off-by: Nithin Dabilpuram --- doc/guides/nics/features/octeontx2.ini | 1 + doc/guides/nics/features/octeontx2_vec.ini | 1 + drivers/net/octeontx2/Makefile | 1 + drivers/net/octeontx2/meson.build | 1 + drivers/net/octeontx2/otx2_ethdev.c | 20 ++ drivers/net/octeontx2/otx2_ethdev.h | 23 +++ drivers/net/octeontx2/otx2_flow_ctrl.c | 230 +++++++++++++++++++++ 7 files changed, 277 insertions(+) create mode 100644 drivers/net/octeontx2/otx2_flow_ctrl.c diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini index 18daccc49..ba7fdc868 100644 --- a/doc/guides/nics/features/octeontx2.ini +++ b/doc/guides/nics/features/octeontx2.ini @@ -21,6 +21,7 @@ RSS hash = Y RSS key update = Y RSS reta update = Y Inner RSS = Y +Flow control = Y Packet type parsing = Y Rx descriptor status = Y Basic stats = Y diff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini index ccf4dac42..b909918ce 100644 --- a/doc/guides/nics/features/octeontx2_vec.ini +++ b/doc/guides/nics/features/octeontx2_vec.ini @@ -21,6 +21,7 @@ RSS hash = Y RSS key update = Y RSS reta update = Y Inner RSS = Y +Flow control = Y Packet type parsing = Y Rx descriptor status = Y Basic stats = Y diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile index 00f61c354..1d3788466 100644 --- a/drivers/net/octeontx2/Makefile +++ b/drivers/net/octeontx2/Makefile @@ -37,6 +37,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \ otx2_stats.c \ otx2_lookup.c \ otx2_ethdev.c \ + otx2_flow_ctrl.c \ otx2_ethdev_irq.c \ otx2_ethdev_ops.c \ otx2_ethdev_debug.c \ diff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build index eb5206ea1..e4fcac763 100644 --- a/drivers/net/octeontx2/meson.build +++ b/drivers/net/octeontx2/meson.build @@ -10,6 +10,7 @@ sources = files( 'otx2_stats.c', 'otx2_lookup.c', 'otx2_ethdev.c', + 'otx2_flow_ctrl.c', 'otx2_ethdev_irq.c', 'otx2_ethdev_ops.c', 'otx2_ethdev_debug.c', diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index 0df487983..97e0e3465 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -216,6 +216,14 @@ nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev, aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT); aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR); + /* TX pause frames enable flowctrl on RX side */ + if (dev->fc_info.tx_pause) { + /* Single bpid is allocated for all rx channels for now */ + aq->cq.bpid = dev->fc_info.bpid[0]; + aq->cq.bp = NIX_CQ_BP_LEVEL; + aq->cq.bp_ena = 1; + } + /* Many to one reduction */ aq->cq.qint_idx = qid % dev->qints; @@ -1069,6 +1077,7 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev) /* Free the resources allocated from the previous configure */ if (dev->configured == 1) { + otx2_nix_rxchan_bpid_cfg(eth_dev, false); oxt2_nix_unregister_queue_irqs(eth_dev); nix_set_nop_rxtx_function(eth_dev); rc = nix_store_queue_cfg_and_then_release(eth_dev); @@ -1122,6 +1131,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev) goto free_nix_lf; } + rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true); + if (rc) { + otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc); + goto free_nix_lf; + } + /* * Restore queue config when reconfigure followed by * reconfigure and no queue configure invoked from application case. @@ -1300,6 +1315,8 @@ static const struct eth_dev_ops otx2_eth_dev_ops = { .pool_ops_supported = otx2_nix_pool_ops_supported, .get_module_info = otx2_nix_get_module_info, .get_module_eeprom = otx2_nix_get_module_eeprom, + .flow_ctrl_get = otx2_nix_flow_ctrl_get, + .flow_ctrl_set = otx2_nix_flow_ctrl_set, }; static inline int @@ -1501,6 +1518,9 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; + /* Disable nix bpid config */ + otx2_nix_rxchan_bpid_cfg(eth_dev, false); + /* Free up SQs */ for (i = 0; i < eth_dev->data->nb_tx_queues; i++) { otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]); diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index 8fbd4532e..fad151b54 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -68,6 +68,9 @@ #define NIX_TX_NB_SEG_MAX 9 #endif +/* Apply BP when CQ is 75% full */ +#define NIX_CQ_BP_LEVEL (25 * 256 / 100) + #define CQ_OP_STAT_OP_ERR 63 #define CQ_OP_STAT_CQ_ERR 46 @@ -150,6 +153,14 @@ struct otx2_npc_flow_info { uint16_t flow_max_priority; }; +struct otx2_fc_info { + enum rte_eth_fc_mode mode; /**< Link flow control mode */ + uint8_t rx_pause; + uint8_t tx_pause; + uint8_t chan_cnt; + uint16_t bpid[NIX_MAX_CHAN]; +}; + struct otx2_eth_dev { OTX2_DEV; /* Base class */ MARKER otx2_eth_dev_data_start; @@ -196,6 +207,7 @@ struct otx2_eth_dev { struct otx2_nix_tm_node_list node_list; struct otx2_nix_tm_shaper_profile_list shaper_profile_list; struct otx2_rss_info rss_info; + struct otx2_fc_info fc_info; uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS]; uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS]; struct otx2_npc_flow_info npc_flow; @@ -350,6 +362,17 @@ int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev); int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr); +/* Flow Control */ +int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev, + struct rte_eth_fc_conf *fc_conf); + +int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, + struct rte_eth_fc_conf *fc_conf); + +int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb); + +int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev); + /* Lookup configuration */ void *otx2_nix_fastpath_lookup_mem_get(void); diff --git a/drivers/net/octeontx2/otx2_flow_ctrl.c b/drivers/net/octeontx2/otx2_flow_ctrl.c new file mode 100644 index 000000000..bd3cda594 --- /dev/null +++ b/drivers/net/octeontx2/otx2_flow_ctrl.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include "otx2_ethdev.h" + +int +otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + struct otx2_fc_info *fc = &dev->fc_info; + struct otx2_mbox *mbox = dev->mbox; + struct nix_bp_cfg_req *req; + struct nix_bp_cfg_rsp *rsp; + int rc; + + if (otx2_dev_is_vf(dev)) + return 0; + + if (enb) { + req = otx2_mbox_alloc_msg_nix_bp_enable(mbox); + req->chan_base = 0; + req->chan_cnt = 1; + req->bpid_per_chan = 0; + + rc = otx2_mbox_process_msg(mbox, (void *)&rsp); + if (rc || req->chan_cnt != rsp->chan_cnt) { + otx2_err("Insufficient BPIDs, alloc=%u < req=%u rc=%d", + rsp->chan_cnt, req->chan_cnt, rc); + return rc; + } + + fc->bpid[0] = rsp->chan_bpid[0]; + } else { + req = otx2_mbox_alloc_msg_nix_bp_disable(mbox); + req->chan_base = 0; + req->chan_cnt = 1; + + rc = otx2_mbox_process(mbox); + + memset(fc->bpid, 0, sizeof(uint16_t) * NIX_MAX_CHAN); + } + + return rc; +} + +int +otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev, + struct rte_eth_fc_conf *fc_conf) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + struct cgx_pause_frm_cfg *req, *rsp; + struct otx2_mbox *mbox = dev->mbox; + int rc; + + if (otx2_dev_is_vf(dev)) + return -ENOTSUP; + + req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(mbox); + req->set = 0; + + rc = otx2_mbox_process_msg(mbox, (void *)&rsp); + if (rc) + goto done; + + if (rsp->rx_pause && rsp->tx_pause) + fc_conf->mode = RTE_FC_FULL; + else if (rsp->rx_pause) + fc_conf->mode = RTE_FC_RX_PAUSE; + else if (rsp->tx_pause) + fc_conf->mode = RTE_FC_TX_PAUSE; + else + fc_conf->mode = RTE_FC_NONE; + +done: + return rc; +} + +static int +otx2_nix_cq_bp_cfg(struct rte_eth_dev *eth_dev, bool enb) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + struct otx2_fc_info *fc = &dev->fc_info; + struct otx2_mbox *mbox = dev->mbox; + struct nix_aq_enq_req *aq; + struct otx2_eth_rxq *rxq; + int i, rc; + + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { + rxq = eth_dev->data->rx_queues[i]; + + aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); + if (!aq) { + /* The shared memory buffer can be full. + * flush it and retry + */ + otx2_mbox_msg_send(mbox, 0); + rc = otx2_mbox_wait_for_rsp(mbox, 0); + if (rc < 0) + return rc; + + aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); + if (!aq) + return -ENOMEM; + } + aq->qidx = rxq->rq; + aq->ctype = NIX_AQ_CTYPE_CQ; + aq->op = NIX_AQ_INSTOP_WRITE; + + if (enb) { + aq->cq.bpid = fc->bpid[0]; + aq->cq_mask.bpid = ~(aq->cq_mask.bpid); + aq->cq.bp = NIX_CQ_BP_LEVEL; + aq->cq_mask.bp = ~(aq->cq_mask.bp); + } + + aq->cq.bp_ena = !!enb; + aq->cq_mask.bp_ena = ~(aq->cq_mask.bp_ena); + } + + otx2_mbox_msg_send(mbox, 0); + rc = otx2_mbox_wait_for_rsp(mbox, 0); + if (rc < 0) + return rc; + + return 0; +} + +static int +otx2_nix_rx_fc_cfg(struct rte_eth_dev *eth_dev, bool enb) +{ + return otx2_nix_cq_bp_cfg(eth_dev, enb); +} + +int +otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, + struct rte_eth_fc_conf *fc_conf) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + struct otx2_fc_info *fc = &dev->fc_info; + struct otx2_mbox *mbox = dev->mbox; + struct cgx_pause_frm_cfg *req; + uint8_t tx_pause, rx_pause; + int rc = 0; + + if (otx2_dev_is_vf(dev)) + return -ENOTSUP; + + if (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time || + fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) { + otx2_info("Flowctrl parameter is not supported"); + return -EINVAL; + } + + if (fc_conf->mode == fc->mode) + return 0; + + rx_pause = (fc_conf->mode == RTE_FC_FULL) || + (fc_conf->mode == RTE_FC_RX_PAUSE); + tx_pause = (fc_conf->mode == RTE_FC_FULL) || + (fc_conf->mode == RTE_FC_TX_PAUSE); + + /* Check if TX pause frame is already enabled or not */ + if (fc->tx_pause ^ tx_pause) { + if (otx2_dev_is_A0(dev) && eth_dev->data->dev_started) { + /* on A0, CQ should be in disabled state + * while setting flow control configuration. + */ + otx2_info("Stop the port=%d for setting flow control\n", + eth_dev->data->port_id); + return 0; + } + /* TX pause frames, enable/disable flowctrl on RX side. */ + rc = otx2_nix_rx_fc_cfg(eth_dev, tx_pause); + if (rc) + return rc; + } + + req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(mbox); + req->set = 1; + req->rx_pause = rx_pause; + req->tx_pause = tx_pause; + + rc = otx2_mbox_process(mbox); + if (rc) + return rc; + + fc->tx_pause = tx_pause; + fc->rx_pause = rx_pause; + fc->mode = fc_conf->mode; + + return rc; +} + +int +otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + struct otx2_fc_info *fc = &dev->fc_info; + struct rte_eth_fc_conf fc_conf; + + if (otx2_dev_is_vf(dev)) + return 0; + + memset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf)); + /* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW + * by AF driver, update those info in PMD structure. + */ + otx2_nix_flow_ctrl_get(eth_dev, &fc_conf); + + if (fc_conf.mode != fc->mode && fc->mode == RTE_FC_NONE) { + /* PMD disables HW flow control in the initial application's call + * to dev_start(), application uses flow_ctrl_set() API to set + * flow control later. + */ + fc->mode = fc_conf.mode; + fc_conf.mode = RTE_FC_NONE; + } + + /* To avoid Link credit deadlock on A0, disable Tx FC if it's enabled */ + if (otx2_dev_is_A0(dev) && + (fc_conf.mode == RTE_FC_FULL || fc_conf.mode == RTE_FC_RX_PAUSE)) { + fc_conf.mode = + (fc_conf.mode == RTE_FC_FULL || + fc_conf.mode == RTE_FC_TX_PAUSE) ? + RTE_FC_TX_PAUSE : RTE_FC_NONE; + } + + return otx2_nix_flow_ctrl_set(eth_dev, &fc_conf); +}