From patchwork Fri Dec 14 13:18:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 48878 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 692341BC15; Fri, 14 Dec 2018 14:19:45 +0100 (CET) Received: from mail-lj1-f195.google.com (mail-lj1-f195.google.com [209.85.208.195]) by dpdk.org (Postfix) with ESMTP id 095B61BBD1 for ; Fri, 14 Dec 2018 14:19:24 +0100 (CET) Received: by mail-lj1-f195.google.com with SMTP id e5-v6so4878333lja.4 for ; Fri, 14 Dec 2018 05:19:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=isZOwDkti5VGYwBG5C/Qw9PnGUvXYXNeyO9Me7QkaOg=; b=fgqnmNTaNhSR1LOOAAgROh3uR0KJKL+63YD8k7OuK7k0vkskTg5F4tdRAqZg5fSRda vtO9sIDXjtKb7NLq2B0B0cvz16EZVTV2rR11Ty7QGekcZR8YBX7nDPOnPer3xCJQNNsy l9pr+CJDEuWgeWGm6YBEMnD+MRxjouzUqS0M/728efRNmL5U6afpTRpTAFMxP0QRgD4Q vqUcvgPFoUFZV0Y9fdalDqZGqNFUwQMlRvdy8GY6XU94x0occMtMwVrRF2lBYzAMEtDN ktRMmUVJhauTumij9tGOsj1Aj5lAWeDn7/UhD2Tl+25tytZynzaf3s2Be5avNaylC1sA 8JFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=isZOwDkti5VGYwBG5C/Qw9PnGUvXYXNeyO9Me7QkaOg=; b=fE96GVyKk9B58lPVWLw1Peo9uGY9n5065Y03Z9ZXmy66hma3RNZd/N5M/5AMAk6Ewx oVxWPeRU7H7rrs2HSfMyUHzDsDU5NZS2wygyAlXHJ76fyS7JhPboHTiFrVeO1im8f/to ogSOK+GxaK0wT9lNroJb8xjYsSH52RE6YU9pWLHehVvqzNvdPmYnRF4l+X5mpXZWxx1N JeIuQ7r2pYel14Z25ZciLBJvGLsE+uua6TlVgvOLRbM0OK2D+i2+78Sn+1TTCzYqv7Nc dp9W26885egx9P3rbycz3NLZbQijxKC6Mv9ecFVrdJuvZFMYJZ0s1I+xqOAsnkKsRg/G PWvA== X-Gm-Message-State: AA+aEWY7cVwIvhBPxBGqOAD+IlU16dfVfKE14Hi2y2HX/sDTfqOW3dbB hwQVKo811c/9HM89QyDPcnuidqK4tN8= X-Google-Smtp-Source: AFSGD/WtUiD7Xydm3BPejmAX/E8sL4kQajQZOv270cAHbgfOJNCz5nld2tMgWQ2bszaZF4wTiTRWzg== X-Received: by 2002:a2e:8256:: with SMTP id j22-v6mr1853755ljh.40.1544793564100; Fri, 14 Dec 2018 05:19:24 -0800 (PST) Received: from mkPC.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id o25sm873884lfd.29.2018.12.14.05.19.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Dec 2018 05:19:23 -0800 (PST) From: Michal Krawczyk To: dev@dpdk.org Cc: gtzalik@dpdk.org, mw@dpdk.org, matua@amazon.com, rk@semihalf.com, Michal Krawczyk Date: Fri, 14 Dec 2018 14:18:46 +0100 Message-Id: <20181214131846.22439-21-mk@semihalf.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20181214131846.22439-1-mk@semihalf.com> References: <20181214131846.22439-1-mk@semihalf.com> Subject: [dpdk-dev] [PATCH 20/20] net/ena: release of the ENAv2 driver (v2.0.0) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The ENAv2 is introducing many new features, mainly the LLQ feature (Low Latency Queue) which allows the device to process packets faster and as a result, the latency is noticeably lower. The second major feature is configurable depth of hw queues where Rx and Tx can be reconfigured independently and maximum depth of Rx queue is 8k. The release also includes many bug fixes and minor new features, like improved statistics counters and extended statistics. Driver is still compatible with ENAv1 device. Signed-off-by: Michal Krawczyk --- drivers/net/ena/ena_ethdev.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index b336102ba..eba3e4c16 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -53,9 +53,9 @@ #include #include -#define DRV_MODULE_VER_MAJOR 1 -#define DRV_MODULE_VER_MINOR 1 -#define DRV_MODULE_VER_SUBMINOR 1 +#define DRV_MODULE_VER_MAJOR 2 +#define DRV_MODULE_VER_MINOR 0 +#define DRV_MODULE_VER_SUBMINOR 0 #define ENA_IO_TXQ_IDX(q) (2 * (q)) #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)