From patchwork Mon Jun 4 12:09:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 40612 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C297C5F16; Mon, 4 Jun 2018 14:10:02 +0200 (CEST) Received: from mail-lf0-f68.google.com (mail-lf0-f68.google.com [209.85.215.68]) by dpdk.org (Postfix) with ESMTP id C93535B2E for ; Mon, 4 Jun 2018 14:10:00 +0200 (CEST) Received: by mail-lf0-f68.google.com with SMTP id o9-v6so24808046lfk.1 for ; Mon, 04 Jun 2018 05:10:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=L49gIBrEEi+jGFFEfozrhbfqa/NpCOen7oyyPxSOBKQ=; b=qR/vNol2RGMIyBSsdvCZsXimWXED9rWBgzaaun9tKH802AeRxjDAAa3Vd1LtqTKoPY bOUuLxNOO9Zq5pfQ8TEIAUgNpgXTCQQvy9umhui0KWB4CZvkSb8lj5q0YRPLnGIpFlLy Rffjza2U6WyUWLUKx5EpE99xoSw5AbU7u1/7N+elzjBHdoaD4/lYDRPYNnupsRpmpIY5 sSV7n+urse9GJnLiOyay0dV1hAIi5h8OktoR41kL+xlBE8QEu0bINuY72x+UF3hBGtiF CYFS1/a2+41Ku/A9onOJuRRPbIsTbXlbaGPZUjsrIUy+5LY83SPK0WTY8my68iZ18Ypf tfIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=L49gIBrEEi+jGFFEfozrhbfqa/NpCOen7oyyPxSOBKQ=; b=BzT4/L0HPAv9Yg9fLLjxYjZlzLZuBmdo/6g3tiEjtLGrRx7WsyU6cJVEOWlGoo1uWc 0yRmbNZArcj5xr2DbUau+GvTG0teT0wfyh8/BZSHQykKCXACrWADabi/bomDiG90NBAH 8/MRw7ZsNW8hnxXDakHalrZWdH0ch+LXyuyh9CKTVr6/YAe54W8ew0S36qzntpWe3mpZ FBsWllHq1/UCU8LNpQ4Jrnc7p9/FKU5jVVTMYOlRmYj7cWnfdhursHCemfzjDCOhEkje 5WjaAeJhfBIMwxblvL0zZ+gKSza8i8D95R0F+T1E6+3qGn7AUdb6+7eylUgny9CDJVBr WK2w== X-Gm-Message-State: ALKqPwcfbseDr8F/tYEws5yxW4h7eYN7j2Ojsb1ZvajIidwU3cLXL4xt +lSHvbZ632X8LSURYogbeKOyeA== X-Google-Smtp-Source: ADUXVKKbMymsltESQCY+5S7LYQQeNyronkoQgf244Xt3040sYO87qAgLqYY/dR47a/PX63GUnncY7A== X-Received: by 2002:a19:8e93:: with SMTP id a19-v6mr12333297lfl.25.1528114200458; Mon, 04 Jun 2018 05:10:00 -0700 (PDT) Received: from mkPC.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id g23-v6sm3817415lfi.49.2018.06.04.05.09.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jun 2018 05:09:59 -0700 (PDT) From: Michal Krawczyk To: Marcin Wojtas , Michal Krawczyk , Guy Tzalik , Evgeny Schemeilin Cc: dev@dpdk.org, matua@amazon.com Date: Mon, 4 Jun 2018 14:09:38 +0200 Message-Id: <20180604120955.17319-1-mk@semihalf.com> X-Mailer: git-send-email 2.14.1 Subject: [dpdk-dev] [PATCH v2 10/26] net/ena: add watchdog and keep alive AENQ handler X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Keep alive is executing AENQ interrupt periodically. It allows to check health of the device and trigger reset event if the device will stop responding. To check for the state of the device, the DPDK application must call rte_timer_manage(). Signed-off-by: Michal Krawczyk --- drivers/net/ena/ena_ethdev.c | 58 ++++++++++++++++++++++++++++++++++++++++++-- drivers/net/ena/ena_ethdev.h | 9 +++++++ 2 files changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index ce05883d9..98f1b6c0a 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -249,6 +249,7 @@ static int ena_rss_reta_query(struct rte_eth_dev *dev, uint16_t reta_size); static int ena_get_sset_count(struct rte_eth_dev *dev, int sset); static void ena_interrupt_handler_rte(void *cb_arg); +static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); static const struct eth_dev_ops ena_dev_ops = { .dev_configure = ena_dev_configure, @@ -979,6 +980,7 @@ static int ena_start(struct rte_eth_dev *dev) { struct ena_adapter *adapter = (struct ena_adapter *)(dev->data->dev_private); + uint64_t ticks; int rc = 0; rc = ena_check_valid_conf(adapter); @@ -1002,6 +1004,13 @@ static int ena_start(struct rte_eth_dev *dev) ena_stats_restart(dev); + adapter->timestamp_wd = rte_get_timer_cycles(); + adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; + + ticks = rte_get_timer_hz(); + rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), + ena_timer_wd_callback, adapter); + adapter->state = ENA_ADAPTER_STATE_RUNNING; return 0; @@ -1012,6 +1021,8 @@ static void ena_stop(struct rte_eth_dev *dev) struct ena_adapter *adapter = (struct ena_adapter *)(dev->data->dev_private); + rte_timer_stop_sync(&adapter->timer_wd); + adapter->state = ENA_ADAPTER_STATE_STOPPED; } @@ -1358,7 +1369,8 @@ static int ena_device_init(struct ena_com_dev *ena_dev, } aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | - BIT(ENA_ADMIN_NOTIFICATION); + BIT(ENA_ADMIN_NOTIFICATION) | + BIT(ENA_ADMIN_KEEP_ALIVE); aenq_groups &= get_feat_ctx->aenq.supported_groups; rc = ena_com_set_aenq_config(ena_dev, aenq_groups); @@ -1388,6 +1400,26 @@ static void ena_interrupt_handler_rte(void *cb_arg) ena_com_aenq_intr_handler(ena_dev, adapter); } +static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, + void *arg) +{ + struct ena_adapter *adapter = (struct ena_adapter *)arg; + struct rte_eth_dev *dev = adapter->rte_dev; + + if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) + return; + + /* Within reasonable timing range no memory barriers are needed */ + if ((rte_get_timer_cycles() - adapter->timestamp_wd) >= + adapter->keep_alive_timeout) { + RTE_LOG(ERR, PMD, "The ENA device is not responding - " + "performing device reset..."); + adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; + _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, + NULL); + } +} + static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) { struct rte_pci_device *pci_dev; @@ -1490,6 +1522,10 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) ena_com_set_admin_polling_mode(ena_dev, false); ena_com_admin_aenq_enable(ena_dev); + if (adapters_found == 0) + rte_timer_subsystem_init(); + rte_timer_init(&adapter->timer_wd); + adapters_found++; adapter->state = ENA_ADAPTER_STATE_INIT; @@ -1803,6 +1839,16 @@ static void ena_update_hints(struct ena_adapter *adapter, /* convert to usec */ adapter->ena_dev.mmio_read.reg_read_to = hints->mmio_read_timeout * 1000; + + if (hints->driver_watchdog_timeout) { + if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) + adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; + else + // Convert msecs to ticks + adapter->keep_alive_timeout = + (hints->driver_watchdog_timeout * + rte_get_timer_hz()) / 1000; + } } static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, @@ -2022,6 +2068,14 @@ static void ena_notification(void *data, } } +static void ena_keep_alive(void *adapter_data, + __rte_unused struct ena_admin_aenq_entry *aenq_e) +{ + struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; + + adapter->timestamp_wd = rte_get_timer_cycles(); +} + /** * This handler will called for unknown event group or unimplemented handlers **/ @@ -2035,7 +2089,7 @@ static struct ena_aenq_handlers aenq_handlers = { .handlers = { [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, [ENA_ADMIN_NOTIFICATION] = ena_notification, - [ENA_ADMIN_KEEP_ALIVE] = unimplemented_aenq_handler + [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive }, .unimplemented_handler = unimplemented_aenq_handler }; diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 79e9e655d..b44cca23e 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -34,8 +34,10 @@ #ifndef _ENA_ETHDEV_H_ #define _ENA_ETHDEV_H_ +#include #include #include +#include #include "ena_com.h" @@ -50,6 +52,9 @@ #define ENA_MMIO_DISABLE_REG_READ BIT(0) +#define ENA_WD_TIMEOUT_SEC 3 +#define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz()) + struct ena_adapter; enum ena_ring_type { @@ -185,6 +190,10 @@ struct ena_adapter { bool link_status; enum ena_regs_reset_reason_types reset_reason; + + struct rte_timer timer_wd; + uint64_t timestamp_wd; + uint64_t keep_alive_timeout; }; #endif /* _ENA_ETHDEV_H_ */